Datasheet > IW4516BN

IW4516BN

更新时间： 2024-11-14 05:39:55

品牌	Logo	应用领域
IKSEMICON		计数器高压栅
页数	文件大小	规格书
7页	321K
描述
Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS

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数据手册

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IW4516BN 数据手册

TECHNICAL DATA

IW4516B

Presettable Up/Down Counter

High-Voltage Silicon-Gate CMOS

The IW4516B Presettable Binary Up/Down Counter consists of four

synchronously clocked D-type flip-flops (with a gating structure to

provide T-type flip-flop capability) connected as counters. This counter

can be cleared by a high level on the RESET line, and can be preset to any

binary number present on the jam inputs by a high level on the PRESET

ENABLE line.

If the CARRY-IN input is held low, the counter advances up or down

on each positive-going clock transition. Synchronous cascading is

accomplished by connecting all clock inputs in parallel and connecting the

CARRY-OUT of a less significant stage to the CARRY-IN of a more

significant stage.

ORDERING INFORMATION

IW4516BN Plastic

IW4516BD SOIC

The IW4516B can be cascaded in the ripple mode by connecting the

CARRY-OUT to the clock of the next stage. If the UP/DOWN input

changes during a terminal count, the CARRY-OUT must be gated with

the clock, and the UP/DOWN input must change while the clock is high.

This method provides a clean clock signal to the subsequent

counting stage.

T_A= -55° to 125° C for all packages

PIN ASSIGNMENT

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 μA at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

•

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Outputs

Mode

CL CI U/D PE

NO COUNT

COUNT UP

COUNT

DOWN

PRESET

RESET

PIN 16=V_CC

PIN 8= GND

X = don’t care

Rev. 00

12 3 4 5 6 7

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