Datasheet > IW4043BD

IW4043BD

更新时间： 2024-09-25 05:39:55

品牌	Logo	应用领域
IKSEMICON		锁存器高压栅
页数	文件大小	规格书
6页	227K
描述
Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS

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数据手册

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IW4043BD 数据手册

TECHNICAL DATA

IW4043B

Quad 3-State R/S Latches

High-Voltage Silicon-Gate CMOS

The IW4043B types are quad cross-coupled 3-state CMOS NOR

latces. Each latch has a separate Q output and individual SET and RESET

inputs. The Q outputs are controlled by a common ENABLE input. A

logic “1” or high on the ENABLE input connects the latch states to the Q

outputs. A logic “0” or low on the ENABLE input disconnects the latch

states from the Q outputs, resulting in an open circuit condition on the Q

outputs. The open circuit feature allows common busing of the outputs.

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 μA at 18 V over full package-temperature

range; 100 nA at 18 V and 25°C

ORDERING INFORMATION

IW4043BN Plastic

IW4043BD SOIC

T_A= -55° to 125° C for all packages

•

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Outputs

High

Impedance

No change

PIN 13 = NO CONNECTION

PIN 16=V_CC

X = don’t care

PIN 8= GND

Rev. 00

12 3 4 5 6

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