Datasheet > IW4017B

IW4017B

更新时间： 2024-01-25 03:46:09

品牌	Logo	应用领域
伊泰克 - ESTEK		/
页数	文件大小	规格书
6页	222K
描述
5-stageJohnson counter having 10 decode outputs

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数据手册

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IW4017B 数据手册

IW4017B

Description

The IW4017B is 5 – stageJohnson counter having 10 decode outputs. Inputs include a CLOCK, a

pulse

RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides

shaping that allows unlimited clock input pulse rise and fall

times.

The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBITsignal is

low. Counter advancement via the clock line isinhibited when the CLOCK INHIBIT signal is high. A high

RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-

speed operation, 2-input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus

assuring proper counting sequence. The decoded

Outputs are normally low and go high only at their

Y-

C ARR

respective decoded

time slot. Each decoded output remains high for one full clock cycle.

cycles.

Signal completes one cycle every 10 clock input

Features

Pin Assignment



Operating Voltage Range: 3.0 to 18 V

at 18 V over full package-

Maximum input current of 1

temperature range







;

100 nA at 18 V and 25 C

DIP - 16



Noise margin (over full package temperature range):

1.0 V min

2.0 V min

2.5 V min

5.0 V supply

10.0 V supply

15.0 V supply

SOP - 16

Logic Diagram

Package

Function Table

Clock

Reset Output State

Enable

no change

reset counter

Q0=H, Q1-Q9=L,

C0=H

Advance to next

state

no change

Advance to next

state

PIN16 = V_CC

PIN 8 =

Carry Out=H for Q0 ,Q1,Q2,Q3 or Q4=H

Carry Out = L otherwise,

X = don' t care

BEIJING ESTEK ELECTRONICS CO.,LTD

12 3 4 5 6

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