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ISPLSI5256VE-125LF256I PDF预览

ISPLSI5256VE-125LF256I

更新时间： 2024-10-29 03:06:51
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
24页 246K
描述
In-System Programmable 3.3V SuperWIDE High Density PLD

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ISPLSI5256VE-125LF256I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：FBGA-256
针数：256Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.88Is Samacsys：N
其他特性：YES最大时钟频率：87 MHz
系统内可编程：YESJESD-30 代码：S-PBGA-B256
JESD-609代码：e0JTAG BST：YES
长度：17 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：144
宏单元数：256端子数量：256
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 144 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA256,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY电源：2.5/3.3,3.3 V
可编程逻辑类型：EE PLD传播延迟：7.5 ns
认证状态：Not Qualified座面最大高度：2.1 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：17 mm
Base Number Matches：1

ISPLSI5256VE-125LF256I 数据手册

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®
ispLSI 5256VE  
In-System Programmable  
3.3V SuperWIDE™ High Density PLD  
Features  
Functional Block Diagram  
• Second Generation SuperWIDE HIGH DENSITY  
IN-SYSTEM PROGRAMMABLE LOGIC DEVICE  
— 3.3V Power Supply  
Input Bus  
Input Bus  
Boundary  
Scan  
Interface  
Generic  
Logic Block  
Generic  
Logic Block  
— User Selectable 3.3V/2.5V I/O  
— 12000 PLD Gates / 256 Macrocells  
— Up to 144 I/O Pins  
— 256 Registers  
— High-Speed Global Interconnect  
— SuperWIDE Generic Logic Block (32 Macrocells) for  
Optimum Performance  
— SuperWIDE Input Gating (68 Inputs) for Fast  
Counters, State Machines, Address Decoders, etc.  
— PCB Efficient Ball Grid Array (BGA) Package Options  
— Interfaces with Standard 5V TTL Devices  
Global Routing Pool  
(GRP)  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 165 MHz Maximum Operating Frequency  
— tpd = 6.0 ns Propagation Delay  
— TTL/3.3V/2.5V Compatible Input Thresholds and  
Output Levels  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
Generic  
Logic Block  
Generic  
Logic Block  
— Programmable Speed/Power Logic Path Optimization  
Input Bus  
Input Bus  
• IN-SYSTEM PROGRAMMABLE  
— Increased Manufacturing Yields, Reduced Time-to-  
Market, and Improved Product Quality  
— Reprogram Soldered Devices for Faster Debugging  
ispLSI 5000VE Description  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND  
3.3V IN-SYSTEM PROGRAMMABLE  
The ispLSI 5000VE Family of In-System Programmable  
High Density Logic Devices is based on Generic Logic  
Blocks (GLBs) of 32 registered macrocells and a single  
Global Routing Pool (GRP) structure interconnecting the  
GLBs.  
• ARCHITECTURE FEATURES  
— Enhanced Pin-Locking Architecture with Single-  
Level Global Routing Pool and SuperWIDE GLBs  
— Wrap Around Product Term Sharing Array Supports  
up to 35 Product Terms Per Macrocell  
— Macrocells Support Concurrent Combinatorial and  
Registered Functions  
— Macrocell Registers Feature Multiple Control  
Options Including Set, Reset and Clock Enable  
— Four Dedicated Clock Input Pins Plus Macrocell  
Product Term Clocks  
Outputs from the GLBs drive the Global Routing Pool  
(GRP) between the GLBs. Switching resources are pro-  
vided to allow signals in the Global Routing Pool to drive  
any or all the GLBs in the device. This mechanism allows  
fast, efficient connections across the entire device.  
Each GLB contains 32 macrocells and a fully populated,  
programmable AND-array with 160 logic product terms  
and three extra control product terms. The GLB has 68  
inputs from the Global Routing Pool which are available  
in both true and complement form for every product term.  
The 160 product terms are grouped in 32 sets of five and  
sent into a Product Term Sharing Array (PTSA) which  
allows sharing up to a maximum of 35 product terms for  
a single function. Alternatively, the PTSA can be by-  
passed for functions of five product terms or less. The  
three extra product terms are used for shared controls:  
reset, clock, clock enable and output enable.  
— Programmable I/O Supports Programmable Bus  
Hold, Pull-up, Open Drain and Slew Rate Options  
— Four Global Product Term Output Enables, Two  
Global OE Pins and One Product Term OE per  
Macrocell  
Copyright©2002LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
January 2002  
5256ve_10  
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