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ISPLSI3192-70LQ PDF预览

ISPLSI3192-70LQ

更新时间： 2024-10-29 05:11:51
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
15页 156K
描述
High Density Programmable Logic

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中文翻译

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ISPLSI3192-70LQ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, QFP-240
针数：240Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.85其他特性：YES
最大时钟频率：50 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G240JESD-609代码：e0
JTAG BST：YES长度：32 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：192宏单元数：192
端子数量：240最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 192 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：FQFP封装等效代码：QFP240,1.3SQ,20
封装形状：SQUARE封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：225电源：5 V
可编程逻辑类型：EE PLD传播延迟：18 ns
认证状态：Not Qualified座面最大高度：4.1 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：32 mmBase Number Matches：1

ISPLSI3192-70LQ 数据手册

 浏览型号ISPLSI3192-70LQ的Datasheet PDF文件第2页浏览型号ISPLSI3192-70LQ的Datasheet PDF文件第3页浏览型号ISPLSI3192-70LQ的Datasheet PDF文件第4页浏览型号ISPLSI3192-70LQ的Datasheet PDF文件第5页浏览型号ISPLSI3192-70LQ的Datasheet PDF文件第6页浏览型号ISPLSI3192-70LQ的Datasheet PDF文件第7页 
®
ispLSI 3192  
High Density Programmable Logic  
Features  
Functional Block Diagram  
• HIGH-DENSITY PROGRAMMABLE LOGIC  
— 192 I/O Pins  
— 9000 PLD Gates  
ORP  
F3 F2  
ORP  
F1 F0  
ORP  
E3 E2 E1 E0  
ORP  
Boundary  
Scan  
— 384 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
Global Routing Pool  
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
A0  
A1  
A2  
A3  
D3  
D2  
D1  
D0  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— fmax = 100 MHz Maximum Operating Frequency  
— tpd = 10 ns Propagation Delay  
OR  
Array  
Twin  
GLB  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
OR  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
Array  
• IN-SYSTEM PROGRAMMABLE  
— Supports ISP™ or ispJTAG™ Programming  
— Increased Manufacturing Yields, Reduced Time-to-  
Market, and Improved Product Quality  
B0  
B1  
B2  
B3  
C1 C2  
C0  
C3  
ORP  
ORP  
ORP  
ORP  
— Reprogram Soldered Devices for Faster Debugging  
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE  
0139/3192  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
Description  
The ispLSI 3192 is a High Density Programmable Logic  
Device containing 384 Registers, 192 Universal I/O pins,  
five Dedicated Clock Input Pins, twelve Output Routing  
Pools (ORP), and a Global Routing Pool (GRP) which  
allows complete inter-connectivity between all of these  
elements. The ispLSI 3192 features 5-Volt in-system  
programmability and in-system diagnostic capabilities.  
The ispLSI 3192 offers non-volatile reprogrammability of  
the logic, as well as the interconnect to provide truly  
reconfigurable systems.  
— Five Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to Mini-  
mize Switching Noise  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
The basic unit of logic on the ispLSI 3192 device is the  
TwinGenericLogicBlock(TwinGLB)labelledA0,A1...F3.  
There are a total of 24 of these Twin GLBs in the ispLSI  
3192 device. Each Twin GLB has 24 inputs, a program-  
mable AND array and two OR/Exclusive-OR Arrays, and  
eight outputs which can be configured to be either com-  
binatorial or registered. All Twin GLB inputs come from  
the GRP.  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©2002LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
June 2002  
3192_08  
1
1234567...15

中文翻译

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