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ISPLSI2128VL-135LQ160 PDF预览

ISPLSI2128VL-135LQ160

更新时间: 2024-10-28 22:15:47
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
17页 215K
描述
2.5V In-System Programmable SuperFAST⑩ High Density PLD

ISPLSI2128VL-135LQ160 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, QFP-160
针数:160Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82Is Samacsys:N
其他特性:YES最大时钟频率:95 MHz
系统内可编程:YESJESD-30 代码:S-PQFP-G160
JESD-609代码:e0JTAG BST:YES
长度:28 mm湿度敏感等级:3
专用输入次数:4I/O 线路数量:128
宏单元数:128端子数量:160
最高工作温度:70 °C最低工作温度:
组织:4 DEDICATED INPUTS, 128 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP160,1.2SQ封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):225
电源:2.5 V可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:4.1 mm子类别:Programmable Logic Devices
最大供电电压:2.7 V最小供电电压:2.3 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:28 mm
Base Number Matches:1

ISPLSI2128VL-135LQ160 数据手册

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®
ispLSI 2128VL  
2.5V In-System Programmable  
SuperFAST™ High Density PLD  
Features  
Functional Block Diagram*  
• SuperFAST HIGH DENSITY IN-SYSTEM  
PROGRAMMABLE LOGIC  
Output Routing Pool (ORP)  
D7 D6  
D5  
D4  
Output Routing Pool (ORP)  
D2  
D1  
D0  
— 6000 PLD Gates  
D3  
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs  
— 128 Registers  
— High Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
— 100% Functional, JEDEC and Pinout Compatible  
with ispLSI 2128V and 2128VE Devices  
A0  
A1  
C7  
C6  
D
Q
Q
Q
Q
A2  
A3  
C5  
C4  
D
D
D
Logic  
Array  
A4  
A5  
C3  
C2  
GLB  
• 2.5V LOW VOLTAGE 2128 ARCHITECTURE  
— Interfaces with Standard 3.3V Devices (Inputs and  
I/Os are 3.3V Tolerant)  
— 125 mA Typical Active Current  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
A6  
A7  
C1  
C0  
Global Routing Pool (GRP)  
fmax = 150 MHz Maximum Operating Frequency  
tpd = 6.0 ns Propagation Delay  
B0  
B1  
B2  
B3  
B5  
B6  
B7  
B4  
Output Routing Pool (ORP)  
Output Routing Pool (ORP)  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
0139A/2128VL  
*128 I/O version shown  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
Description  
• IN-SYSTEM PROGRAMMABLE  
The ispLSI 2128VL is a High Density Programmable  
Logic Device available in 128 and 64 I/O-pin versions.  
The device contains 128 Registers, eight Dedicated  
Input pins, three Dedicated Clock Input pins, two dedi-  
cated Global OE input pins and a Global Routing Pool  
(GRP). The GRP provides complete interconnectivity  
between all of these elements. The ispLSI 2128VL fea-  
tures in-system programmability through the Boundary  
Scan Test Access Port (TAP) and is 100% IEEE 1149.1  
Boundary Scan Testable. The ispLSI 2128VL offers non-  
volatile reprogrammability of the logic, as well as the  
interconnect to provide truly reconfigurable systems.  
— 2.5V In-System Programmability (ISP™) Using  
Boundary Scan Test Access Port (TAP)  
— Open-Drain Output Option for Flexible Bus Interface  
Capability, Allowing Easy Implementation of Wired-  
OR Bus Arbitration Logic  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
— Reprogram Soldered Devices for Faster Prototyping  
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE  
• THE EASE OF USE AND FAST SYSTEM SPEED OF  
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control  
— Flexible Pin Placement  
The basic unit of logic on the ispLSI 2128VL device is the  
Generic Logic Block (GLB). The GLBs are labeled A0, A1  
.. D7 (see Figure 1). There are a total of 32 GLBs in the  
ispLSI 2128VL device. Each GLB is made up of four  
macrocells. Each GLB has 18 inputs, a programmable  
AND/OR/ExclusiveORarray, andfouroutputswhichcan  
be configured to be either combinatorial or registered.  
Inputs to the GLB come from the GRP and dedicated  
inputs. All of the GLB outputs are brought back into the  
GRP so that they can be connected to the inputs of any  
GLB on the device.  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-  
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL  
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING  
— Superior Quality of Results  
— Tightly Integrated with Leading CAE Vendor Tools  
— Productivity Enhancing Timing Analyzer, Explore  
Tools, Timing Simulator and ispANALYZER™  
— PC and UNIX Platforms  
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
September 2000  
2128vL_02  
1

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