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ISPLSI2032-110LJI

更新时间： 2024-11-14 05:11:51

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
15页	145K
描述
In-System Programmable High Density PLD

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数据手册

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ispLSI 2032/A

In-System Programmable High Density PLD

Features

Functional Block Diagram

• ENHANCEMENTS

— ispLSI 2032A is Fully Form and Function Compatible

to the ispLSI 2032, with Identical Timing

Specifcations and Packaging

— ispLSI 2032A is Built on an Advanced 0.35 Micron

E²CMOS^®Technology

• HIGH DENSITY PROGRAMMABLE LOGIC

Global Routing Pool

(GRP)

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

Logic

Array

GLB

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 180 MHz Maximum Operating Frequency

— tpd = 5.0 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

0139Bisp/2000

Description

The ispLSI 2032 and 2032A are High Density Program-

mable Logic Devices. The devices contain 32 Registers,

32 Universal I/O pins, two Dedicated Input Pins, three

Dedicated Clock Input Pins, one dedicated Global OE

input pin and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 2032 and 2032A feature 5V in-

system programmability and in-system diagnostic

capabilities. The ispLSI 2032 and 2032A offer non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1 .. A7

(Figure 1). There are a total of eight GLBs in the ispLSI

2032 and 2032A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

January 2002

2032_10

12 3 4 5 6 7...15

中文翻译

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与ISPLSI2032-110LJI相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI2032-110LJN	LATTICE	获取价格	EE PLD, 13ns, CMOS, PQCC44, PLASTIC, LCC-44
ISPLSI2032-110LT	LATTICE	获取价格	EE PLD, 14.5ns, 32-Cell, CMOS, PQFP48, TQFP-48
ISPLSI2032-110LT44	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032-110LT44I	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032-110LT48	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032-110LT48I	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032-110LTN48	LATTICE	获取价格	EE PLD, 13ns, CMOS, PQFP48, TQFP-48
ISPLSI2032-135LJ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI2032-135LJ44	LATTICE	获取价格	EE PLD, 12ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
ISPLSI2032-135LJI	LATTICE	获取价格	In-System Programmable High Density PLD

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