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ISPLSI1032-60LT

更新时间： 2024-02-20 09:11:00

品牌	Logo	应用领域
莱迪思 - LATTICE		可编程逻辑
页数	文件大小	规格书
19页	259K
描述
High-Density Programmable Logic

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技术参数
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ISPLSI1032-60LT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20	针数：	100
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.82
其他特性：	YES	最大时钟频率：	38 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0	JTAG BST：	NO
长度：	14 mm	湿度敏感等级：	3
专用输入次数：	4	I/O 线路数量：	64
宏单元数：	128	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	4 DEDICATED INPUTS, 64 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP100,.63SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	240
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	25 ns	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

ISPLSI1032-60LT 数据手册

Specifications ispLSI and pLSI 1032

ispLSI and pLSI 1032

High-Density Programmable Logic

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— High Speed Global Interconnect

— 6000 PLD Gates

— 64 I/O Pins, Eight Dedicated Inputs

— 192 Registers

Output Routing Pool

D7 D6 D5 D4 D3 D2 D1 D0

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Fast Random Logic

— Security Cell Prevents Unauthorized Copying

• HIGH PERFORMANCE E CMOS TECHNOLOGY

Logic

Array

GLB

^—fmax = 90 MHz Maximum Operating Frequency

—^—t^fp^md^a=^{x =}12⁶⁰ns^MP^Hr^zop^foa^rg^Iaⁿt^dio^un^stD^rie^al^la^ay^{nd Military/883 Devices}

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E²CMOS Technology

— 100% Tested

Global Routing Pool (GRP)

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

— Reprogram Soldered Devices for Faster Prototyping

• COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEX-

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

Description

The ispLSI and pLSI 1032 are High-Density Program-

mable Logic Devices containing 192 Registers, 64

Universal I/O pins, eight Dedicated Input pins, four Dedi-

cated Clock Input pins and a Global Routing Pool (GRP).

The GRP provides complete interconnectivity between

all of these elements. The ispLSI 1032 features 5-Volt in-

system programming and in-system diagnostic

capabilities. It is the first device which offers non-volatile

"on-the-fly" reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems. It is

architecturally and parametrically compatible to the pLSI

1032 device, but multiplexes four of the dedicated input

pins to control in-system programming.

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispLSI AND pLSI DEVELOPMENT TOOLS

pDS^®Software

— Easy to Use PC Windows™ Interface

— Boolean Logic Compiler

— Manual Partitioning

— Automatic Place and Route

— Static Timing Table

The basic unit of logic on the ispLSI and pLSI 1032

devices is the Generic Logic Block (GLB). The GLBs are

labeled A0, A1 .. D7 (see figure 1). There are a total of

32 GLBs in the ispLSI and pLSI 1032 devices. Each GLB

has 18 inputs, a programmable AND/OR/XOR array, and

four outputs which can be configured to be either combi-

natorial or registered. Inputs to the GLB come from the

GRP and dedicated inputs. All of the GLB outputs are

brought back into the GRP so that they can be connected

to the inputs of any other GLB on the device.

ispDS+™ Software

— Industry Standard, Third Party Design

Environments

— Schematic Capture, State Machine, HDL

— Automatic Partitioning and Place and Route

— Comprehensive Logic and Timing Simulation

— PC and Workstation Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

February 1997

1996 ISP Encyclopedia

1032_02

1996 ISP Encyclopedia

12 3 4 5 6 7...19

中文翻译

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ISPLSI1032-60LT 替代型号

型号	品牌	替代类型	描述	数据表
ISPLSI1032E-70LTI	LATTICE	完全替代	High-Density Programmable Logic
ISPLSI1032-80LT	LATTICE	完全替代	In-System Programmable High Density PLD
ISPLSI1032E-100LT	LATTICE	完全替代	In-System Programmable High Density PLD

与ISPLSI1032-60LT相关器件

型号	品牌	获取价格	描述	数据表
ISPLSI1032-60LT/833	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-60LTI	LATTICE	获取价格	High-Density Programmable Logic
ISPLSI1032-80	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-80LG	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-80LG/833	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-80LGI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-80LJ	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-80LJ/833	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-80LJI	LATTICE	获取价格	In-System Programmable High Density PLD
ISPLSI1032-80LT	LATTICE	获取价格	In-System Programmable High Density PLD

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