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ISPLSI1016E-100LT44I

更新时间: 2024-11-06 02:53:43
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莱迪思 - LATTICE /
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描述
In-System Programmable High Density PLD

ISPLSI1016E-100LT44I 数据手册

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®
ispLSI 1016E  
In-System Programmable High Density PLD  
Features  
Functional Block Diagram  
• HIGH-DENSITY PROGRAMMABLE LOGIC  
— 2000 PLD Gates  
— 32 I/O Pins, Four Dedicated Inputs  
— 96 Registers  
— High-Speed Global Interconnect  
— Wide Input Gating for Fast Counters, State  
Machines, Address Decoders, etc.  
— Small Logic Block Size for Random Logic  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
D
D
D
D
Q
Q
Q
Q
Logic  
Array  
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY  
GLB  
fmax = 125 MHz Maximum Operating Frequency  
tpd = 7.5 ns Propagation Delay  
— TTL Compatible Inputs and Outputs  
— Electrically Erasable and Reprogrammable  
— Non-Volatile  
Global Routing Pool (GRP)  
— 100% Tested at Time of Manufacture  
— Unused Product Term Shutdown Saves Power  
CLK  
• IN-SYSTEM PROGRAMMABLE  
— In-System Programmable (ISP™) 5V Only  
— Increased Manufacturing Yields, Reduced Time-to-  
Market and Improved Product Quality  
0139C1-isp  
Description  
— Reprogram Soldered Device for Faster Prototyping  
• OFFERS THE EASE OF USE AND FAST SYSTEM  
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY  
OF FIELD PROGRAMMABLE GATE ARRAYS  
— Complete Programmable Device Can Combine Glue  
Logic and Structured Designs  
— Enhanced Pin Locking Capability  
— Three Dedicated Clock Input Pins  
— Synchronous and Asynchronous Clocks  
— Programmable Output Slew Rate Control to  
Minimize Switching Noise  
The ispLSI 1016E is a High Density Programmable Logic  
Device containing 96 Registers, 32 Universal I/O pins,  
four Dedicated Input pins, three Dedicated Clock Input  
pins, one Global OE input pin and a Global Routing Pool  
(GRP). The GRP provides complete interconnectivity  
between all of these elements. The ispLSI 1016E offers  
5Vnon-volatilein-systemprogrammabilityofthelogic,as  
well as the interconnect to provide truly reconfigurable  
systems. A functional superset of the ispLSI 1016  
architecture, the ispLSI 1016E device adds a new global  
output enable pin.  
— Flexible Pin Placement  
— Optimized Global Routing Pool Provides Global  
Interconnectivity  
The basic unit of logic on the ispLSI 1016E device is the  
Generic Logic Block (GLB). The GLBs are labeled A0,  
A1...B7 (see Figure 1). There are a total of 16 GLBs in the  
ispLSI 1016E device. Each GLB has 18 inputs, a  
programmable AND/OR/Exclusive OR array, and four  
outputswhichcanbeconfiguredtobeeithercombinatorial  
or registered. Inputs to the GLB come from the GRP and  
dedicated inputs. All of the GLB outputs are brought back  
into the GRP so that they can be connected to the inputs  
of any other GLB on the device.  
Copyright©2002LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
January 2002  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
1016e_08  
1

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