Datasheet > ISP1703A

ISP1703A

更新时间： 2024-11-24 10:13:43

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
2页	134K
描述
ISP1703A

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中文翻译

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数据手册

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ISP1703A 数据手册

NXP family of ULPI

Hi-Speed USB transceivers

ISP150x, ISP170x

Best-in-class ULPI transceivers for

mobile and portable applications

Designed for use with ASICs, FPGAs, and system chipsets that interface with the physical layer

of the USB connection, these ﬁrst- and second-generation transceivers provide reliable USB

performance in a low-pin format and support a full range of portable applications,

including mobile phones.

Key features

Input power supply: 3.0 to 4.5 V

Charger detection

Fully compliant with:

- Universal Serial Bus Speciﬁcation Revision 2.0

- On-The-Go Supplement to the USB Speciﬁcation

Revision 1.2

ULPI SDR and DDR modes available

UART pass-through mode

Space-saving packages (HVQFN32/24, TFBGA36, WLCSP25)

- UTMI+ Low Pin Interface (ULPI) Speciﬁcation Revision 1.1

High-speed (480 Mbps), full-speed (12 Mbps) and low-speed

(1.5 Mbps) data rates

NXP offers two generations of UTMI+ Low Pin Interface (ULPI)

Hi-Speed USB transceivers. Both generations build on

the proven, fully compliant NXP architecture for ULPI, which

allows USB ASICs, FPGAs, and system chipsets to interface

with the physical layer of the USB connection. All offer very

small form factor and very low power.

Interfaces to Hi-Speed USB host, peripheral, and dual-role

device cores

Highly optimized ULPI-compliant interface

- 60-MHz, 4- or 8-bit interface between ASIC and transceiver

- Integrated PLL supports 60-MHz input clock and a wide

spectrum of crystal or clock frequencies.

- Fully programmable ULPI-compliant register set

- Internal power-on reset circuit

The core architecture supports high-speed (480 Mbps),

full-speed (12 Mbps), and low-speed (1.5 Mbps) data rates,

and includes a highly optimized interface that operates at

60 MHz and uses only eight (DDR) or twelve (SDR) signals

between the ASIC and the transceiver.

Integrated resistors: 45-Ω high-speed terminations, 1.5-kΩ

full-speed device pull-up, and 15-kΩ host terminations

Guaranteed V_BUSimpedance of 80 to 100 kΩ for

ISP1702, ISP1703

An integrated phase-locked loop (PLL) supports a 60-MHz

input clock and a range of crystal or clock frequencies.

The architecture also includes a fully programmable,

Support for bus reset, suspend, resume, and high-speed

detection handshake (chirp)

Low suspend current (50 µA) and low power-down mode

current (0.5 µA)

中文翻译

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与ISP1703A相关器件

型号	品牌	获取价格	描述	数据表
ISP1703BUKTS	ETC	获取价格	Ultra-low-power transceiver solutions for mobile and portable applications
ISP1704	ETC	获取价格	Ultra-low-power transceiver solutions for mobile and portable applications
ISP1705AET	NXP	获取价格	IC UNIVERSAL SERIAL BUS CONTROLLER, PBGA36, 3.5 X 3.5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT,
ISP1705AET,118	NXP	获取价格	IC UNIVERSAL SERIAL BUS CONTROLLER, PBGA36, 3.5 X 3.5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT,
ISP1705HN,518	NXP	获取价格	USB Bus Controller, CMOS, PQCC36, 5 X 5 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-22
ISP1760	NXP	获取价格	Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1760BE	NXP	获取价格	Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1760ET	PHILIPS	获取价格	Bus Controller, PBGA128,
ISP1760ET-T	NXP	获取价格	Hi-Speed Universal Serial Bus host controller for embedded applications - Application: pri
ISP1761	NXP	获取价格	Hi-Speed Universal Serial Bus On-The-Go controller

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