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ISO721DUBR PDF预览

ISO721DUBR

更新时间： 2024-01-24 03:04:51
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德州仪器 - TI /
页数 文件大小 规格书
29页 677K
描述
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS

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ISO721DUBR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：0.62Is Samacsys：N
其他特性：ALSO OPERATES FROM 4.5 TO 5.5 V SUPPLY接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：4.905 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.895 mmBase Number Matches：1

ISO721DUBR 数据手册

 浏览型号ISO721DUBR的Datasheet PDF文件第2页浏览型号ISO721DUBR的Datasheet PDF文件第3页浏览型号ISO721DUBR的Datasheet PDF文件第4页浏览型号ISO721DUBR的Datasheet PDF文件第5页浏览型号ISO721DUBR的Datasheet PDF文件第6页浏览型号ISO721DUBR的Datasheet PDF文件第7页 
ISO721, ISO721M  
ISO722, ISO722M  
www.ti.com  
SLLS629J –JANUARY 2006–REVISED JULY 2010  
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS  
Check for Samples: ISO721, ISO721M, ISO722, ISO722M  
1
FEATURES  
DESCRIPTION  
23  
•
4000-V(peak) Isolation, 560-Vpeak VIORM  
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)  
IEC 61010-1, IEC 60950-1 and CSA  
Approved  
The ISO721, ISO721M, ISO722, and ISO722M are  
digital isolators with a logic input and output buffer  
separated by a silicon dioxide (SiO2) insulation  
barrier. This barrier provides galvanic isolation of up  
to 4000 V. Used in conjunction with isolated power  
supplies, these devices prevent noise currents on a  
data bus or other circuits from entering the local  
ground, and interfering with or damaging sensitive  
circuitry.  
–
50 kV/µs Transient Immunity, Typical  
•
Signaling Rate 0 Mbps to 150 Mbps  
–
–
Low Propagation Delay  
Low Pulse Skew (Pulse-Width Distortion)  
•
•
•
•
•
Low-Power Sleep Mode  
High Electromagnetic Immunity  
Low Input-Current Requirement  
Failsafe Output  
A binary input signal is conditioned, translated to a  
balanced signal, then differentiated by the capacitive  
isolation barrier. Across the isolation barrier,  
a
differential comparator receives the logic transition  
information, then sets or resets a flip-flop and the  
output circuit accordingly. A periodic update pulse is  
sent across the barrier to ensure the proper dc level  
of the output. If this dc-refresh pulse is not received  
for more than 4 ms, the input is assumed to be  
unpowered or not being actively driven, and the  
failsafe circuit drives the output to a logic-high state.  
Drop-In Replacement for Most Opto and  
Magnetic Isolators  
APPLICATIONS  
•
Industrial Fieldbus  
–
–
–
–
Modbus  
Profibus  
DeviceNet™ Data Buses  
Smart Distributed Systems ( SDS™)  
•
•
•
Computer Peripheral Interface  
Servo Control Interface  
Data Acquisition  
FUNCTION DIAGRAM  
Isolation Barrier  
DC Channel  
+
_
Filter  
Pulse Width  
Demodulation  
OSC  
+
PWM  
V
ref  
_
+
Carrier Detect  
POR  
POR  
BIAS  
ISO722  
Only  
+
_
Data MUX  
AC Detect  
3-State  
EN  
Input  
+
Filter  
IN  
V
ref  
_
+
OUT  
Output Buffer  
AC Channel  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
SDS is a trademark of Honeywell.  
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2010, Texas Instruments Incorporated  
 
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ISO721DUBR 替代型号

型号 品牌 替代类型 描述 数据表
ISO721DUB TI

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