Datasheet > ISM67-62A9H2-212.500MHZ

ISM67-62A9H2-212.500MHZ

更新时间： 2023-08-15 00:00:00

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描述
LVPECL Output Clock Oscillator,

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ISM67-62A9H2-212.500MHZ 数据手册

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3.2 mm x 2.5 mm Ceramic Package SMD Oscillator,

LVMOS / LVPECL / LVDS

ISM67 Series

Product Features

Small Surface Mount Package

Fast Sample Delivery

Pb Free/ RoHS Compliant

Leadfree Processing

Applications

3.20±0.10

Marking

xDSL

Ethernet/LAN/WAN

Optical modules

Clock and data recovery

FPGA/ASIC

Broadcast Video

Wireless Base Stations

Sonet /SDH

2.50±0.10

1.00±0.15

WiMAX/WLAN

Backplanes

Server and Storage

GPON

.60

TYP

Frequency

LVCMOS

LVPECL

LVDS

10.000MHz to 250.000MHz

10.000MHz to 1500.000MHz

1.30

TYP

Output Level

LVCMOS

LVPECL

LVDS

1.60

Logic “0” = 10% of Vcc max, Logic “1” = 90% of Vcc min

Logic “0”= Vcc-1.62V max., Logic “1” = 1.02 V min

VOD=(Diff. Output) 350mV Typ.

2.30

Duty Cycle

LVMOS

LVPECL

LVDS

50% ±5% @ 50% of Vcc

50% ±5% @ 50%*

.70

.90

1.80

Rise / Fall Time

LVCMOS

LVPECL

LVDS

2.0 ns max. (10% to 90%)*

0.8 ns max. (20% to 80%)*

.90

Output Load

LVCMOS

LVPECL

LVDS

.80

15pF

Suggested Land Pattern

50  to Vcc - 2.0 VDC

RL=100 /CL= 5pF

See Table Below

+3.30 VDC ± 5%, +2.50 VDC ± 5%

±3.0 ppm max per year

HCMOS = 45 mA max

LVPECL = 90 mA max

LVDS = 35 mA max

0.9 ps typical

PIN CONNECTIONS

Enable/Disable

Frequency Stability

Supply Voltage (Vcc)

Aging

PIN 1

or N/C

Enable/Disable

or N/C

PIN 2

Current

PIN 3

PIN 4

Ground

Output

Comp. Output

or N/C

PIN 5

PIN 6

Phase Jitter (RMS)

(12kHz to 20MHz)

Voltage Supply

Operating Temp. Range

Storage Temp. Range

See Table Below

-40 C to +85 C

Dimension Units: mm

Part Number Guide

Sample Part Number:

ISM67–31A9H2–155.520

Package

Input

Voltage

3 = 3.3V

6 = 2.5V

Operating

Stability

(in ppm)

F = 20

Output

Enable / Disable

Complimentary

Ouput (Pin 5) **

Frequency

Temperature

1 = 0 C to +70 C

2 = -40 C to +85 C

3 = -20 C to +70 C

3 = LVCMOS

8 = LVDS

H = Enable (Pin 1)

K = Enable (Pin 2)

1 = N.C.

2 = Output

A = 25

-155.520 MHz

ISM67

9 = LVPECL

B = 50

NOTE: A 0.01 µF bypass capacitor is recommended between V_DD(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of

waveform. ** Available on LVDS and LVPECL ouput only.

Rev: 03/10/15_A

Page 1 of 3

ILSI America Phone 775-851-8880 ● Fax 775-851-8882 ●email: e-mail@ilsiamerica.com ●

www.ilsiamerica.com

Specifications subject to change without notice

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