Datasheet > ISLA214S50IR48EV1Z

ISLA214S50IR48EV1Z

更新时间： 2024-11-16 11:13:11

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
41页	1519K
描述
14-Bit, 500/350 MSPS JESD204B High Speed Serial Output ADC

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14-Bit, 500/350 MSPS JESD204B High Speed Serial

Output ADC

ISLA214S50

Features

• JESD204A/B High Speed Data Interface

- JESD204A Compliant

The ISLA214S50 is a series of low-power, high-performance,

14-bit, analog-to-digital converters. Designed with

FemtoCharge™ technology on a standard CMOS process, the

series supports sampling rates of up to 500MSPS. The

ISLA214S50 is part of a pin-compatible family of 12-, 14-, and

16-bit A/Ds with maximum sample rates ranging from

125MSPS to 500MSPS. The family minimizes power

consumption while providing state-of-the-art dynamic

performance.

- JESD204B Device Subclass 0 Compliant

- JESD204B Device Subclass 2 Compatible

- Up to 3 JESD204 Output Lanes Running up to 4.375Gbps

- Highly Configurable JESD204 Transmitter

• Multiple Chip Time Alignment and Deterministic Latency

Support (JESD204B Device Subclass 2)

The device utilizes two time-interleaved 250MSPS unit ADCs to

achieve the ultimate sample rate of 500MSPS. A single

500MHz conversion clock is presented to the converter, and all

interleave clocking is managed internally. The proprietary

Intersil Interleave Engine (I2E) performs automatic correction

of offset, gain, and sample time mismatches between the unit

ADCs to optimize performance.

• SPI Programmable Debugging Features and Test Patterns

• 48-pin QFN 7mmx7mm Package

Key Specifications

• SNR @ 500/350MSPS

73.1/74.1 dBFS f = 30MHz

71.0/71.6 dBFS f = 363MHz

The ISLA214S50 offers a highly configurable, JESD204B-

compliant, high speed serial output link. The link offers data

rates up to 4.375 Gbps per lane and multiple packing modes.

The link can be configured to use two or three lanes to

transmit the conversion data, allowing for flexibility in the

receiver design. The JESD204 transmitter also provides

deterministic latency and multi-chip time alignment support to

satisfy complex synchronization requirements.

• SFDR @ 500/350MSPS

87/87 dBc f = 30MHz

78/81 dBc f = 363MHz

• Total Power Consumption: 1060mW @ 500MSPS

Applications

• Radar and Satellite Antenna Array Processing

• Broadband Communications and Microwave Receivers

• High-Performance Data Acquisition

• Communications Test Equipment

• High-Speed Medical Imaging

A serial peripheral interface (SPI) port allows for extensive

configurability of the ADC and its JESD204B transmitter

including access to its built-in link and transport-layer test

patterns as well as the programmable clock divider, enabling

2x harmonic clocking.

The ISLA214S50 is available in a space-saving 7mmx7mm 48

Ld QFN package. The package features a thermal pad for

improved thermal performance and is specified over the full

industrial temperature range (-40°C to +85°C)

Pin-Compatible Family

SPEED

PRODUCT

MODEL

ISLA214S50

ISLA214S35

RESOLUTION

(MSPS)

AVAILABILITY

500

350

Now

Soon

FIGURE 1. SERDES DATA EYE AT 4.375Gbps

December 21, 2011

FN7973.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

12 3 4 5 6 7...41

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