DATASHEET
ISLA112P25M
Low Power 12-Bit, 250MSPS ADC
FN7646
Rev 1.00
November 17, 2011
The ISLA112P25MREP is a low-power 12-bit, 250MSPS
analog-to-digital converter. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process.
Features
• Programmable Gain, Offset and Skew Control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of
various parameters such as gain and offset.
• Over-Range Indicator
• Selectable Clock Divider: 1, 2 or 4
• Clock Phase Selection
Digital output data is presented in selectable LVDS or
CMOS formats. The ISLA112P25MREP is available in a
72 Ld QFN package with an exposed paddle. Operating
from a 1.8V supply, performance is specified over the
full military temperature range (-55°C to +125°C).
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data
Format
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
Applications
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• Pb-Free (RoHS Compliant)
VID Features
• High-Performance Data Acquisition
• Communications Test Equipment
• Specifications per DSCC VID V62/10609
• Full Military Temperature Electrical Performance
from -55°C to +125°C
Key Specifications
• Controlled Baseline with One Wafer Fabrication Site
and One Assembly/Test Site
• SNR = 62.7dBFS for f = 105MHz (-1dBFS)
IN
• SFDR = 67dBc for f = 105MHz (-1dBFS)
IN
• Total Power Consumption
- 310mW @ 250MSPS (SDR Mode)
- 234mW @ 250MSPS (DDR Mode)
• Full Homogeneous Lot Processing in Wafer Fab
• No Combination of Wafer Fabrication Lots in
Assembly
• Full Traceability Through Assembly and Test by
• Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS
Component
Block Diagram
CLKP
CLKN
CLKOUTP
CLKOUTN
CLOCK
GENERATION
D[11:0]P
VINP
12-BIT
250 MSPS
ADC
D[11:0]N
DIGITAL
SHA
ERROR
CORRECTION
ORP
VINN
VCM
ORN
LVDS/CMOS
OUTFMT
+
–
1.25V
DRIVERS
SPI
CONTROL
OUTMODE
FN7646 Rev 1.00
November 17, 2011
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