DATASHEET
ISLA110P50
10-Bit, 500MSPS A/D Converter
FN7606
Rev.3.0
Jul 6, 2021
The ISLA110P50 is a low-power, high-performance, 500MSPS
analog-to-digital converter designed with Renesas’ proprietary
FemtoCharge™ technology on a standard CMOS process. The
ISLA110P50 is part of a pin-compatible portfolio of 8, 10 and
12-bit A/Ds. This device is an upgrade of the KAD551XP-50
product family and is pin similar.
Features
• 1.15GHz Analog Input Bandwidth
• 90fs Clock Jitter
• Automatic Fine Interleave Correction Calibration
• Multiple Chip Time Alignment Support via the Synchronous
Clock Divider Reset
The device utilizes two time-interleaved 250MSPS unit A/Ds to
achieve the ultimate sample rate of 500MSPS. A single
500MHz conversion clock is presented to the converter, and all
interleave clocking is managed internally. The proprietary
Interleave Engine (I2E) performs automatic fine correction of
offset, gain, and sample time skew mismatches between the
unit A/Ds to optimize performance. No external interleaving
algorithm is required.
• Programmable Gain, Offset and Skew Control
• Over-Range Indicator
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue continuous
calibration commands as well as configure many dynamic
parameters.
• Programmable Test Patterns and Internal Temperature
Sensor
Key Specifications
• SNR = 60.6dBFS for f = 190MHz (-1dBFS)
IN
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA110P50 is available in a 72 Ld QFN package
with an exposed paddle. Performance is specified over the full
industrial temperature range (-40°C to +85°C).
• SFDR = 80dBc for f = 190MHz (-1dBFS)
IN
• Total Power Consumption = 441mW
Applications
• Radar and Electronic/Signal Intelligence
• Broadband Communications
• High-Performance Data Acquisition
TABLE 1. PIN-COMPATIBLE FAMILY
SPEED
(MSPS)
MODEL
RESOLUTION
ISLA112P50
ISLA110P50
ISLA118P50
12
10
8
500
500
500
CLKP
CLKN
CLKOUTP
CLKOUTN
CLOCK
MANAGEMENT
10- BIT
250MSPS
ADC
D[9:0]P
D[9:0]N
SHA
VREF
ORP
ORN
DIGITAL
ERROR
VINP
VINN
Gain/ Offset/Skew
Adjustments
I2E
CORRECTION
OUTFMT
OUTMODE
10
- BIT
VCM
SHA
250MSPS
ADC
VREF
1.25V
+
–
SPI
CONTROL
FIGURE 1A. BLOCK DIAGRAM
FN7606 Rev.3.0
Jul 6, 2021
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