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ISL73005SEH

更新时间： 2024-11-27 14:57:51
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
46页 1455K
描述
Radiation Hardened Dual Output Point-of-Load, Integrated Synchronous Buck and Low Dropout Regulator

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ISL73005SEH 数据手册

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Datasheet  
ISL70005SEH, ISL73005SEH  
Radiation Hardened Dual Output Point-of-Load, Integrated Synchronous Buck and Low Dropout  
Regulator  
The ISL70005SEH and ISL73005SEH are radiation  
hardened dual output Point-of-Load (POL) regulators  
combining the high efficiency of a synchronous buck  
regulator with the low noise of a Low Dropout (LDO)  
Features  
• Dual output regulator: sync buck and LDO  
• Independent EN, SS, and PG indicators  
regulator. They are suited for systems with 3.3V or 5V  
power buses and can support continuous output load  
currents of 3A for the buck regulator and ±1A for the  
LDO.  
• ±1% reference voltage  
• 1A current sourcing/sinking capability on LDO  
• External clock synchronization: 100kHz to 1MHz  
• Full military temperature range operation  
The buck regulator uses a voltage mode control  
architecture and switches at a resistor adjustable  
frequency of 100kHz to 1MHz. Externally adjustable  
loop compensation allows for an optimum balance  
between stability and output dynamic performance.  
The internal synchronous power switches are  
optimized for high efficiency and excellent thermal  
performance.  
○ T = -55°C to +125°C  
A
○ T = -55°C to +150°C  
J
• Radiation acceptance testing - ISL70005SEH  
○ HDR (50-300rad(Si)/s): 100krad(Si)  
○ LDR (0.01rad(Si)/s): 75krad(Si)  
• Radiation acceptance testing - ISL73005SEH  
○ LDR (0.01rad(Si)/s): 75krad(Si)  
The LDO is completely configurable independent of  
the switching regulator. It uses NMOS pass devices  
and separate chip bias voltage (L_VCC) to drive its  
gate, enabling the LDO to operate with a very low  
voltage at the L_VIN input. The LDO can sink and  
source up to 1A continuously, making it an ideal  
choice to power DDR memory.  
• SEE hardness (see test report)  
2
○ No SEB or SEL at LET 86.4MeV•cm /mg  
2
○ SET at LET 86.4MeV•cm /mg <±3% ΔV  
OUT  
2
○ No SEFI at LET 43MeV•cm /mg  
The ISL70005SEH and ISL73005SEH are available in  
a space saving 28 Ld ceramic dual flat-pack package  
or in die form. They are specified to operate across a  
• Electrically screened to DLA SMD 5962-19209  
Applications  
temperature range of T = -55°C to +125°C.  
A
• Point-of-load for low power FPGA core, auxiliary  
and I/O supply voltages  
• DDR memory power for VDDQ and VTT rails  
• Distributed power system of satellite payloads  
ISL70005SEH, ISL73005SEH  
Buck Regulator  
0.915  
0.910  
0.905  
0.900  
3.3V or 5V  
VDDQ = 1.8V  
B_PVINx B_LXx  
VDDQ  
VTT = 0.9V  
L_VIN  
L_OUT  
LDO Regulator  
DDR Memory  
Controller  
R
T
DDR  
Memory  
L_VCC = B_VCC = 5V  
L_VIN = 1.8V  
0.895  
R
S
L_EA+ = 0.9V  
0.890  
-1.5  
-1.0  
-0.5  
0.0  
0.5  
1.0  
1.5  
LDO Current (A)  
Figure 1. Power Solution for DDR2 Memory  
Figure 2. LDO Load Regulation; DDR2 Configuration  
R34DS0008EU0103 Rev.1.03  
Jul 28, 2022  
Page 1 of 45  
© 2019-2022 Renesas Electronics  
1234567...46

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