ISL6537A
®
Data Sheet
February 9, 2005
FN9143.3
ACPI Regulator/Controller for
Features
Dual Channel DDR Memory Systems
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR V
- PWM Regulator for GMCH Core
- LDO Regulator for CPU/GMCH V Termination
- LDO Regulator for DAC
The ISL6537A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
DDQ
TT
supply V
DDQ
during S0/S1 and S3 states. During S0/S1 state,
a fully integrated sink-source regulator generates an accurate
(V /2) high current V voltage without the need for a
TT
DDQ
TT
negative supply. A buffered version of the V
/2 reference is
. A second PWM controller, which requires
DDQ
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
provided as V
REF
external MOSFET drivers, is available for regulation of the
GMCH Core voltage. An LDO controller is also integrated for
• Integrated V
Buffer
REF
the CPU V termination voltage regulation and the DAC.
TT
• V
PWM Controller Drives Low Cost N-Channel
DDQ
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
indicates that the GMCH and CPU V termination voltage
TT
is within spec and operational.
• OCP on the V
DDQ
• Integrated Thermal Shutdown Protection
• Pb-Free Available (RoHS Compliant)
Switching Regulator
All outputs, except VDAC, have undervoltage protection.
The switching regulator also has overvoltage and
overcurrent protection. Thermal shutdown is integrated.
Pinout
ISL6537A (QFN)
Applications
TOP VIEW
•
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
•
28 27 26 25 24 23 22
Graphics cards - GPU and memory supplies
• ASIC power supplies
1
2
3
4
5
6
7
21
20
19
5VSBY
DRIVE3
FB3
• Embedded processor and I/O supplies
• DSP supplies
S3#
P12V
PWM4
GND
29
GND
18 FB4
17
Ordering Information
TEMP. RANGE
PKG. DWG.
#
L28.6x6
L28.6x6
DDR_VTT
DDR_VTT
VDDQ
COMP4
PART NUMBER
(°C)
PACKAGE
28 Ld 6x6 QFN
16 COMP
15 FB
ISL6537ACR
0 to 70
0 to 70
ISL6537ACRZ
(See Note)
28 Ld 6x6 QFN
(Pb-free)
8
9
10 11 12 13 14
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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