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ISL6265A PDF预览

ISL6265A

更新时间: 2023-12-20 18:46:07
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瑞萨 - RENESAS /
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24页 1122K
描述
Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265A 数据手册

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DATASHEET  
ISL6265A  
FN6884  
Rev 0.00  
May 11, 2009  
Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable  
Mobile CPUs  
The ISL6265A is a multi-output controller with embedded  
gate drivers. A single-phase controller powers the  
Northbridge (VDDNB) portion of the CPU. The two  
Features  
• Core Configuration Flexibility  
- Dual Plane, Single-Phase Controllers  
- Uniplane, Two-Phase Controller  
remaining controller channels can be configured for  
two-phase or individual single-phase outputs. For uniplane  
CPU applications, the ISL6265A is configured as a  
two-phase buck converter. This allows the controller to  
interleave channels to effectively double the output voltage  
ripple frequency, and thereby reduce output voltage ripple  
amplitude with fewer components, lower component cost,  
reduced power dissipation, and smaller area. For dual-plane  
processors, the ISL6265A can be configured as independent  
single-phase controllers powering VDD0 and VDD1.  
• Precision Voltage Regulators  
- 0.5% System Accuracy Over-temperature  
• Voltage Positioning with Adjustable Load Line and Offset  
• Internal Gate Drivers with 2A Driving Capability  
• Differential Remote CPU Die Voltage Sensing  
• Core Differential Current Sensing: DCR or Resistor  
• Northbridge Lossless rDS(ON) Current Sensing  
The heart of the ISL6265A is the patented R3 Technology™,  
Intersil’s Robust Ripple Regulator modulator. Compared with  
the traditional buck regulator, the R3 Technologyhas a  
faster transient response. This is due to the R3 modulator  
commanding variable switching frequency during a load  
transient.  
• Serial VID Interface  
- Two Wire Clock and Data Bus  
- Supports High-Speed I2C  
- 0.500V to 1.55V in 12.5mV Steps  
- Supports PSI_L Power-Saving Mode  
• Core Outputs Feature Phase Shedding with PSI_L  
• Adjustable Output-Voltage Offset  
The Serial VID Interface (SVI) allows dynamic adjustment of  
the Core and Northbridge output voltages independently and  
in combination from 0.500V to 1.55V. Core and Northbridge  
output voltages achieve a 0.5% system accuracy  
over-temperature.  
• Digital Soft-Start of all Outputs  
• User Programmable Switching Frequency  
• Static and Dynamic Current Sharing (Uniplane Core)  
• Overvoltage, Undervoltage, and Overcurrent Protection  
• Pb-Free (RoHS compliant)  
A unity-gain differential amplifier is provided for remote CPU  
die sensing. This allows the voltage on the CPU die to be  
accurately regulated per AMD mobile CPU specifications.  
Core output current sensing is realized using lossless  
inductor DCR sensing. All outputs feature overcurrent,  
overvoltage and undervoltage protection.  
Pinout  
ISL6265A  
(48 LD 6X6 TQFN)  
TOP VIEW  
Ordering Information  
TEMP  
PART NUMBER  
(Note)  
PART  
MARKING  
RANGE  
(°C)  
PACKAGE  
(Pb-Free)  
PKG.  
DWG. #  
48 47 46 45 44 43 42 41 40 39 38 37  
ISL6265AHRTZ  
6265A HRTZ -10 to +100 48Ld6x6TQFN L48.6x6  
BOOT_NB  
BOOT0  
UGATE0  
PHASE0  
PGND0  
LGATE0  
PVCC  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
OFS/VFIXEN  
PGOOD  
PWROK  
SVD  
ISL6265AHRTZ-T* 6265A HRTZ -10 to +100 48 Ld 6x6 TQFN L48.6x6  
Tape and Reel  
3
4
*Please refer to TB347 for details on reel specifications.  
5
SVC  
NOTE: These Intersil Pb-free plastic packaged products employ  
special Pb-free material sets, molding compounds/die attach materials,  
and 100% matte tin plate plus anneal (e3 termination finish, which is  
RoHS compliant and compatible with both SnPb and Pb-free soldering  
operations). Intersil Pb-free products are MSL classified at Pb-free peak  
reflow temperatures that meet or exceed the Pb-free requirements of  
IPC/JEDEC J STD-020  
49  
6
ENABLE  
RBIAS  
OCSET  
VDIFF0  
FB0  
GND  
7
[BOTTOM]  
LGATE1  
PGND1  
PHASE1  
UGATE1  
BOOT1  
8
9
10  
11  
12  
COMP0  
VW0  
13 14 15 16 17 18 19 20 21 22 23 24  
FN6884 Rev 0.00  
May 11, 2009  
Page 1 of 24  

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