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IS75V16F128GS08-7065BI PDF预览

IS75V16F128GS08-7065BI

更新时间： 2024-11-21 21:12:39
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
52页 262K
描述
SRAM

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IS75V16F128GS08-7065BI 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：compliant风险等级：5.88
JESD-609代码：e0端子面层：Tin/Lead (Sn/Pb)
Base Number Matches：1

IS75V16F128GS08-7065BI 数据手册

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®
IS75V16F128GS32  
ISSI  
3.0 Volt Multi-Chip Package (MCP)  
— 128 Mbit Simultaneous Operation Flash  
Memory and 32 Mbit Pseudo Static RAM  
PRELIMINARY INFORMATION  
January 2003  
MCP FEATURES  
• Erase Algorithms:  
• Power supply voltage 2.7V to 3.3V  
Automatically preprograms/erases the flash memory  
entirely, or by sector  
• High performance:  
Flash: 70ns maximum access time  
• Program Algorithms:  
PSRAM: 65ns maximum access time  
Automatically writes and verifies data at specified  
address  
• Package: 107-ball BGA  
• Operating Temperature: -30C to +85C  
• Hidden ROM Region:  
256 byte with a Factory-serialized secure electronic  
serial number (ESN), which is accessible through a  
command sequence  
FLASH FEATURES  
• Power Dissipation:  
Read Current at 1 Mhz: 4 mA maximum  
Read Current at 5 Mhz:18 mA maximum  
Sleep Mode: 5 µA maximum  
• Data Polling and Toggle Bit:  
Detects the completion of the program or erase cycle  
• Ready-Busy Outputs (RY/BY)  
Detection of program or erase cycle completion for  
each flash chip  
• User Configurable Banks  
Flash 1 (64 Mbit)  
Bank A1: 8Mbit (8KB x 8 and 64KB x 15)  
Bank B1: 24Mbit (64KB x 48)  
Bank C1: 24Mbit (64KB x 48)  
• Over 100,000 write/erase cycles  
• Low supply voltage (Vccf ≤ 2.5V) inhibits writes  
Bank D1: 8Mbit (8KB x 8 and 64KB x 15)  
• WP/ACC input pin:  
If VIL, allows partial protection of boot sectors  
If VIH, allows removal of boot sector protection  
If Vacc, program time is improved  
Flash 2 (64 Mbit)  
Bank A2: 8Mbit (8KB x 8 and 64KB x 15)  
Bank B2: 24Mbit (64KB x 48)  
Bank C2: 24Mbit (64KB x 48)  
Bank D2: 8Mbit (8KB x 8 and 64KB x 15)  
User chooses two virtual banks from a  
combination of four physical banks  
PSRAM FEATURES (32 Mb density)  
• Power Dissipation:  
Operating: 25 mA maximum  
Standby: 110 µA maximum  
• Simultaneous R/W Operations (dual virtual bank):  
Zero latency between read and write operations; Data  
can be programmed or erased in one bank while data  
is simultaneously being read from the other bank  
• Chip Selects: CE1r, CE2r  
• Power down feature using CE2r  
Sleep Mode: 10 µA maximum  
Nap: 65 µA maximum  
8 mbit Partial: 80 µA maximum  
• Low-Power Mode:  
A period of no activity causes flash to enter a  
low-power state  
• Data retention supply voltage: 2.1 V to 3.3V  
• Erase Suspend/Resume:  
Suspends of erase activity to allow a read in the  
same bank  
• Byte data control: LB (DQ0–DQ7), UB  
(DQ8–DQ15)  
• Sector Erase Architecture:  
16 sectors of 4K words each and 126 sectors of 32K words  
each in Word mode. Any combination of sectors, or  
the entire flash can be simultaneously erased  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark  
of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00C  
1
1/06/03  
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