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IS64WV51216BLL-10CTA3 PDF预览

IS64WV51216BLL-10CTA3

更新时间： 2024-11-27 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
20页 198K
描述
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

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IS64WV51216BLL-10CTA3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：PLASTIC, TSOP2-44针数：44
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.63
最长访问时间：10 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e0
长度：18.415 mm内存密度：8388608 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：44字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3 V
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.2 mm最大待机电流：0.05 A
最小待机电流：1.2 V子类别：SRAMs
最大压摆率：0.14 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.4 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10.16 mmBase Number Matches：1

IS64WV51216BLL-10CTA3 数据手册

 浏览型号IS64WV51216BLL-10CTA3的Datasheet PDF文件第2页浏览型号IS64WV51216BLL-10CTA3的Datasheet PDF文件第3页浏览型号IS64WV51216BLL-10CTA3的Datasheet PDF文件第4页浏览型号IS64WV51216BLL-10CTA3的Datasheet PDF文件第5页浏览型号IS64WV51216BLL-10CTA3的Datasheet PDF文件第6页浏览型号IS64WV51216BLL-10CTA3的Datasheet PDF文件第7页 
IS61WV51216ALL  
IS61WV51216BLL  
IS64WV51216BLL  
512K x 16 HIGH-SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH 3.3V SUPPLY  
OCTOBER2009  
FEATURES  
• High-speed access times:  
8, 10, 20 ns  
• High-performance, low-power CMOS process  
• Multiple center power and ground pins for greater  
noise immunity  
DESCRIPTION  
The ISSI IS61WV51216ALL/BLL and IS64WV51216BLL  
are high-speed, 8M-bit static RAMs organized as 512K  
words by 16 bits. It is fabricated using ISSI's high-perform-  
anceCMOStechnology.Thishighlyreliableprocesscoupled  
withinnovativecircuitdesigntechniques,yieldshigh-perfor-  
mance and low power consumption devices.  
• Easy memory expansion with CE and OE op-  
tions  
• CE power-down  
• Fully static operation: no clock or refresh  
required  
When CE is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be  
reduced down with CMOS input levels.  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs, CE and OE. The active LOW  
Write Enable (WE) controls both writing and reading of the  
memory. A data byte allows Upper Byte (UB) and Lower  
Byte (LB) access.  
• TTL compatible inputs and outputs  
• Single power supply  
VDD 1.65V to 2.2V (IS61WV51216ALL)  
speed = 20ns for VDD 1.65V to 2.2V  
VDD 2.4V to 3.6V (IS61/64WV51216BLL)  
speed = 10ns for VDD 2.4V to 3.6V  
speed = 8ns for VDD 3.3V + 5%  
• Packages available:  
The device is packaged in the JEDEC standard 44-pin  
TSOP Type II and 48-pin Mini BGA (9mm x 11mm).  
–
48-ball miniBGA (9mm x 11mm)  
– 44-pin TSOP (Type II)  
• Industrial and Automotive Temperature Support  
• Lead-free available  
• Data control for upper and lower bytes  
FUNCTIONAL BLOCK DIAGRAM  
512K x 16  
MEMORY ARRAY  
A0-A18  
DECODER  
VDD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. F  
10/01/09  
1234567...20

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