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IS61WV25616BLL-10BI-TR PDF预览

IS61WV25616BLL-10BI-TR

更新时间: 2024-09-23 21:09:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
22页 421K
描述
Standard SRAM, 256KX16, 10ns, CMOS, PBGA48

IS61WV25616BLL-10BI-TR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:FBGA, BGA48,6X8,30Reach Compliance Code:compliant
Factory Lead Time:8 weeks风险等级:5.91
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PBGA-B48内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
端子数量:48字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, FINE PITCH并行/串行:PARALLEL
电源:2.5/3.3 V认证状态:Not Qualified
最大待机电流:0.009 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.045 mA
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
Base Number Matches:1

IS61WV25616BLL-10BI-TR 数据手册

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performanceCMOStechnology.Thishighlyreliableprocessꢀ  
                                                                             
IS61WV25616ALL/ALS  
IS61WV25616BLL/BLS  
IS64WV25616BLL/BLS  
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM  
FEBRUARY 2017  
DESCRIPTION  
FEATURES  
TheꢀISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx  
areꢀhigh-speed,ꢀ4,194,304-bitꢀstaticꢀRAMsꢀorganizedꢀasꢀ  
262,144 words by 16 bits.It is fabricated using ISSI's high-  
HIGH SPEED: (IS61/64WV25616ALL/BLL)  
•ꢀ High-speedꢀaccessꢀtime:ꢀ8,ꢀ10,ꢀ20ꢀns  
•ꢀ LowꢀActiveꢀPower:ꢀ85ꢀmWꢀ(typical)  
•ꢀ LowꢀStandbyꢀPower:ꢀ7ꢀmWꢀ(typical)  
coupled with innovative circuit design techniques, yields  
high-performance and low power consumption devices.  
CMOS standby  
LOW POWER: (IS61/64WV25616ALS/BLS)  
•ꢀ High-speedꢀaccessꢀtime:ꢀ25,ꢀ35,ꢀ45ꢀns  
•ꢀ LowꢀActiveꢀPower:ꢀ35ꢀmWꢀ(typical)  
When CE is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be re-  
duced down with CMOS input levels.  
•ꢀ LowꢀStandbyꢀPower:ꢀ0.6ꢀmWꢀ(typical)  
CMOS standby  
Easy memory expansion is provided by using Chip Enable  
and Output Enable inputs, CE and OE.ꢀTheꢀactiveꢀLOWꢀ  
Write Enable (WE) controls both writing and reading of the  
memory. A data byte allows Upper Byte (UB) and Lower  
Byte (LB) access.  
•ꢀ Singleꢀpowerꢀsupply  
— Vdd 1.65V to 2.2V (IS61WV25616Axx)  
— Vddꢀ2.4Vꢀtoꢀ3.6Vꢀ(IS61/64WV25616Bxx)  
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀrequired  
•ꢀ Threeꢀstateꢀoutputs  
Theꢀ IS61WV25616Axx/Bxxꢀ andꢀ IS64WV25616Bxxꢀ areꢀ  
packaged in the JEDEC standard 44-pin 400mil SOJ,  
44-pinꢀTSOPꢀTypeꢀIIꢀꢀandꢀ48-pinꢀMiniꢀBGAꢀ(6mmꢀxꢀ8mm).  
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes  
•ꢀ IndustrialꢀandꢀAutomotiveꢀtemperatureꢀsupport  
•ꢀ Lead-freeꢀavailable  
FUNCTIONAL BLOCK DIAGRAM  
256K x 16  
MEMORY ARRAY  
A0-A17  
DECODER  
VDD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-  
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications  
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. H1  
02/10/2017  

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