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IS61VPS102436A-166TQL PDF预览

IS61VPS102436A-166TQL

更新时间： 2024-11-27 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
21页 235K
描述
1Mb x 36, 2Mb x 18 36Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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IS61VPS102436A-166TQL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：13 weeks 6 days
风险等级：5.71Is Samacsys：N
最长访问时间：3.5 ns其他特性：PIPELINED ARCHITECURE
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：37748736 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.11 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.4 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
Base Number Matches：1

IS61VPS102436A-166TQL 数据手册

 浏览型号IS61VPS102436A-166TQL的Datasheet PDF文件第2页浏览型号IS61VPS102436A-166TQL的Datasheet PDF文件第3页浏览型号IS61VPS102436A-166TQL的Datasheet PDF文件第4页浏览型号IS61VPS102436A-166TQL的Datasheet PDF文件第5页浏览型号IS61VPS102436A-166TQL的Datasheet PDF文件第6页浏览型号IS61VPS102436A-166TQL的Datasheet PDF文件第7页 
IS61VPS102436A IS61LPS102436A  
IS61VPS204818A IS61LPS204818A  
1Mb x 36, 2Mb x 18  
36Mb SYNCHRONOUS PIPELINED,  
SINGLE CYCLE DESELECT STATIC RAM  
MARCH 2008  
DESCRIPTION  
FEATURES  
The ISSI IS61LPS/VPS102436A and IS61LPS/VPS  
204818A are high-speed, low-power synchronous static  
RAMsdesignedtoprovideburstable,high-performancememory  
for communication and networking applications. The  
IS61LPS/VPS102436Aisorganizedas1,048,476words  
by 36 bits. The IS61LPS/VPS204818A is organized as  
2M-word by 18 bits. Fabricated with ISSI's advanced  
CMOS technology, the device integrates a 2-bit burst  
counter,high-speedSRAMcore,andhigh-drivecapability  
outputs into a single monolithic circuit. All synchronous  
inputs pass through registers controlled by a positive-  
edge-triggeredsingleclockinput.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
• Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
therisingedgeoftheclockinput. Writecyclescanbeone  
tofourbyteswideascontrolledbythewritecontrolinputs.  
• Snooze MODE for reduced-power standby  
• Power Supply  
Separatebyteenablesallowindividualbytestobewritten.  
The byte write operation is performed by using the byte  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). In addition, Global  
Write (GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
• JEDEC 100-Pin TQFP and 165-ball PBGA  
packages  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
inputpins.Subsequentburstaddressescanbegenerated  
internally and controlled by the ADV (burst address  
advance) input pin.  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
200  
3.1  
5
166  
3.5  
6
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
200  
166  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc.  
1
Rev. B  
03/27/08  
1234567...21

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与IS61VPS102436A-166TQL相关器件

型号 品牌 获取价格 描述 数据表
IS61VPS102436A-166TQL-TR ISSI

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 		暂无描述
IS61VPS102436A-166TQ-TR ISSI

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 		Standard SRAM, 1MX36, 3.5ns, CMOS, PQFP100
IS61VPS102436B-166B3LI ISSI

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 		IC SRAM 36M PARALLEL 166MHZ
IS61VPS102436B-166B3LI-TR ISSI

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 		IC SRAM 36M PARALLEL 166MHZ
IS61VPS102436B-250B3L ISSI

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 		Cache SRAM, 1MX36, 2.8ns, CMOS, PBGA165, TFBGA-165
IS61VPS102436B-250TQLI ISSI

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 		Cache SRAM, 1MX36, 2.8ns, CMOS, PQFP100, LQFP-100
IS61VPS102436B-250TQLI-TR ISSI

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 		IC SRAM 36M PARALLEL 100LQFP
IS61VPS12832EC-200B2 ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61VPS12832EC-200B2I ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61VPS12832EC-200B2L ISSI

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 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM

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