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IS61VF12836EC-7.5B2LI PDF预览

IS61VF12836EC-7.5B2LI

更新时间： 2024-11-20 19:02:23
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
36页 2441K
描述
Cache SRAM, 128KX36, 7.5ns, CMOS, PBGA119, BGA-119

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IS61VF12836EC-7.5B2LI 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：BGA, BGA119,7X17,50
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.74最长访问时间：7.5 ns
最大时钟频率 (fCLK)：117 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：4718592 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：119字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5 V
认证状态：Not Qualified座面最大高度：3.5 mm
最大待机电流：0.085 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.17 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：10宽度：14 mm
Base Number Matches：1

IS61VF12836EC-7.5B2LI 数据手册

 浏览型号IS61VF12836EC-7.5B2LI的Datasheet PDF文件第2页浏览型号IS61VF12836EC-7.5B2LI的Datasheet PDF文件第3页浏览型号IS61VF12836EC-7.5B2LI的Datasheet PDF文件第4页浏览型号IS61VF12836EC-7.5B2LI的Datasheet PDF文件第5页浏览型号IS61VF12836EC-7.5B2LI的Datasheet PDF文件第6页浏览型号IS61VF12836EC-7.5B2LI的Datasheet PDF文件第7页 
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC  
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC  
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH  
SRAM  
APRIL 2014  
FEATURES  
DESCRIPTION  
The 4Mb product family features high-speed, low-power  
synchronous static RAMs designed to provide burstable,  
high-performance memory for communication and  
networking applications. The IS61(64)LF/VF12836EC are  
organized as 131,072 words by 36bits. The  
IS61(64)LF/VF12832EC are organized as 131,072 words by  
32bits. The IS61(64)LF/VF25618EC are organized as 262,144  
words by 18 bits. Fabricated with ISSI's advanced CMOS  
technology, the device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit. All synchronous inputs pass  
through registers controlled by a positive-edge-triggered  
single clock input.  
Internal self-timed write cycle  
Individual Byte Write Control and Global Write  
Clock controlled, registered address, data and  
control  
Burst sequence control using MODE input  
Three chip enable option for simple depth  
expansion and address pipelining  
Common data inputs and data outputs  
Auto Power-down during deselect  
Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
Snooze MODE for reduced-power standby  
JEDEC 100-pin QFP, 165-ball BGA and 119-ball  
BGA packages  
Separate byte enables allow individual bytes to be written.  
The byte write operation is performed by using the byte  
write enable (/BWE) input combined with one or more  
individual byte write signals (/BWx). In addition, Global  
Write (/GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
Power supply:  
LF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
VF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
JTAG Boundary Scan for BGA packages  
Industrial and Automotive temperature support  
Lead-free available  
Bursts can be initiated with either /ADSP (Address Status  
Processor) or /ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the /ADV (burst address  
advance) input pin.  
Error Detection and Error Correction  
The mode pin is used to select the burst sequence order.  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle time  
-6.5  
6.5  
-7.5  
7.5  
Units  
ns  
tKC  
7.5  
8.5  
ns  
Frequency  
133  
117  
MHz  
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. B  
1
03/19/2014  
1234567...36

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