5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> IS61VF12836A-7.5B2I
IS61VF12836A-7.5B2I PDF预览

IS61VF12836A-7.5B2I

更新时间： 2024-11-20 02:55:19
品牌 Logo 应用领域
美国芯成 - ISSI 内存集成电路静态存储器
页数 文件大小 规格书
25页 166K
描述
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

阅读下载

中文翻译

获取价格

IS61VF12836A-7.5B2I 数据手册

 浏览型号IS61VF12836A-7.5B2I的Datasheet PDF文件第2页浏览型号IS61VF12836A-7.5B2I的Datasheet PDF文件第3页浏览型号IS61VF12836A-7.5B2I的Datasheet PDF文件第4页浏览型号IS61VF12836A-7.5B2I的Datasheet PDF文件第5页浏览型号IS61VF12836A-7.5B2I的Datasheet PDF文件第6页浏览型号IS61VF12836A-7.5B2I的Datasheet PDF文件第7页 
IS61(64)LF12832A IS64VF12832A  
IS61(64)LF12836A IS61(64)VF12836A  
IS61(64)LF25618A IS61(64)VF25618A  
®
ISSI  
128K x 32, 128K x 36, 256K x 18  
4 Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
PRELIMINARY INFORMATION  
AUGUST 2005  
DESCRIPTION  
FEATURES  
The ISSI IS61(64)LF12832A,  
IS64VF12832A,  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are  
high-speed, low-powersynchronousstaticRAMs designed  
to provide burstable, high-performance memory for commu-  
nication and networking applications. The  
IS61(64)LF12832A is organized as 131,072 words by 32  
bits. The IS61(64)LF/VF12836A is organized as 131,072  
words by 36 bits. The IS61(64)LF/VF25618A is organized  
as 262,144 words by 18 bits. Fabricated with ISSI's  
advanced CMOS technology, the device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All syn-  
chronous inputs pass through registers controlled by a  
positive-edge-triggered single clock input.  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
•
Three chip enable option for simple depth expan-  
sion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE) input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW) is  
available for writing all bytes at one time, regardless of the  
byte write controls.  
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VF: VDD 2.5V -5% +10%, VDDQ 2.5V -5% +10%  
• JEDEC 100-Pin TQFP, 119-pin PBGA, and  
165-pin PBGA packages  
• Automotive temperature available  
• Lead-free available  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-6.5  
6.5  
-7.5  
7.5  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
7.5  
8.5  
ns  
Frequency  
133  
117  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. 00A  
1
08/11/05  
1234567...25

中文翻译

下载PDF

与IS61VF12836A-7.5B2I相关器件

型号 品牌 获取价格 描述 数据表
IS61VF12836A-7.5B3 ISSI

获取价格

 		128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF12836A-7.5B3I ISSI

获取价格

 		128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF12836A-7.5TQ ISSI

获取价格

 		128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF12836A-7.5TQI ISSI

获取价格

 		128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF12836EC-6.5B2 ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61VF12836EC-6.5B2I ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61VF12836EC-6.5B2L ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61VF12836EC-6.5B2LI ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61VF12836EC-6.5B3 ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM
IS61VF12836EC-6.5B3I ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM

与IS61VF12836A-7.5B2I相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证