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IS61VF10241A-7.5B2I PDF预览

IS61VF10241A-7.5B2I

更新时间： 2024-11-21 06:45:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
35页 298K
描述
Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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IS61VF10241A-7.5B2I 技术参数

生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.79
最长访问时间：7.5 ns其他特性：PIPELINED ARCHITECTURE, FLOW-THROUGH
JESD-30 代码：R-PBGA-B119长度：22 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：3.5 mm
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM宽度：14 mm

IS61VF10241A-7.5B2I 数据手册

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IS61LF25672A IS61VF25672A  
IS61LF51236A IS61VF51236A  
IS61LF102418A IS61VF102418A  
256K x 72, 512K x 36, 1024K x 18  
18Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
JULY 2010  
DESCRIPTION  
FEATURES  
The ISSI IS61LF/VF25672A, IS61LF/VF51236A and  
IS61LF/VF102418A are high-speed, low-power synchro-  
nous static RAMs designed to provide burstable, high-  
performance memory for communication and networking  
applications. The IS61LF/VF25672A is organized as  
262,144 words by 72 bits. The IS61LF/VF51236A is orga-  
nizedas524,288wordsby36bits.TheIS61LF/VF102418A  
is organized as 1,048,576 words by 18 bits. Fabricated  
with ISSI's advanced CMOS technology, the device inte-  
grates a 2-bit burst counter, high-speed SRAM core, and  
high-drive capability outputs into a single monolithic cir-  
cuit. All synchronous inputs pass through registers con-  
trolled by a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
•
Three chip enable option for simple depth expan-  
sion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE) input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW) is  
available for writing all bytes at one time, regardless of the  
byte write controls.  
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VF: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball  
PBGA and 165-pin PBGA packages.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-6.5  
6.5  
-7.5  
7.5  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
7.5  
8.5  
ns  
Frequency  
133  
117  
MHz  
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.  
1
Rev. K  
07/29/2010  
1234567...35

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