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IS61VF102418A-6.5B3 PDF预览

IS61VF102418A-6.5B3

更新时间： 2024-11-20 02:55:19
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
35页 277K
描述
256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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IS61VF102418A-6.5B3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：10 weeks
风险等级：5.61最长访问时间：6.5 ns
其他特性：PIPELINED ARCHITECTURE, FLOW-THROUGH最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：165字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.06 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.25 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm

IS61VF102418A-6.5B3 数据手册

 浏览型号IS61VF102418A-6.5B3的Datasheet PDF文件第2页浏览型号IS61VF102418A-6.5B3的Datasheet PDF文件第3页浏览型号IS61VF102418A-6.5B3的Datasheet PDF文件第4页浏览型号IS61VF102418A-6.5B3的Datasheet PDF文件第5页浏览型号IS61VF102418A-6.5B3的Datasheet PDF文件第6页浏览型号IS61VF102418A-6.5B3的Datasheet PDF文件第7页 
IS61LF25672A IS61VF25672A  
IS61LF51236A IS61VF51236A  
IS61LF102418A IS61VF102418A  
®
ISSI  
256K x 72, 512K x 36, 1024K x 18  
18Mb SYNCHRONOUS FLOW-THROUGH  
STATIC RAM  
APRIL 2006  
DESCRIPTION  
FEATURES  
The ISSI IS61LF/VF25672A, IS61LF/VF51236A and  
IS61LF/VF102418A are high-speed, low-power synchro-  
nous static RAMs designed to provide burstable, high-  
performance memory for communication and networking  
applications. The IS61LF/VF25672A is organized as  
262,144 words by 72 bits. The IS61LF/VF51236A is orga-  
nizedas524,288wordsby36bits.TheIS61LF/VF102418A  
is organized as 1,048,576 words by 18 bits. Fabricated  
with ISSI's advanced CMOS technology, the device inte-  
grates a 2-bit burst counter, high-speed SRAM core, and  
high-drive capability outputs into a single monolithic cir-  
cuit. All synchronous inputs pass through registers con-  
trolled by a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
•
Three chip enable option for simple depth expan-  
sion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be one  
to four bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE) input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW) is  
available for writing all bytes at one time, regardless of the  
byte write controls.  
LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VF: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-Ball  
PBGA and 165-pin PBGA packages.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
• Lead-free available  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-6.5  
6.5  
-7.5  
7.5  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
7.5  
8.5  
ns  
Frequency  
133  
117  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. E  
04/21/06  
1234567...35

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与IS61VF102418A-6.5B3相关器件

型号 品牌 获取价格 描述 数据表
IS61VF102418A-6.5B3I ISSI

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IS61VF102418A-6.5B3I-TR ISSI

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 		IC SRAM 18M PARALLEL 165TFBGA
IS61VF102418A-6.5B3-TR ISSI

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 		IC SRAM 18M PARALLEL 165TFBGA
IS61VF102418A-6.5TQ ISSI

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IS61VF102418A-6.5TQI ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF102418A-7.5B2 ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF102418A-7.5B2I ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF102418A-7.5B3 ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF102418A-7.5B3I ISSI

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 		256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61VF102418A-7.5B3I-TR ISSI

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 		IC SRAM 18M PARALLEL 165TFBGA

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