Datasheet > IS61SPS25636D-166B

IS61SPS25636D-166B

更新时间： 2024-11-21 06:36:23

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
22页	152K
描述
Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119

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IS61SPS25632T/D IS61LPS25632T/D

IS61SPS25636T/D IS61LPS25636T/D

IS61SPS51218T/D IS61LPS51218T/D ISSI

256K x 32, 256K x 36, 512K x 18

SYNCHRONOUS PIPELINE,

SINGLE-CYCLE DESELECT STATIC RAM

PRELIMINARYINFORMATION

SEPTEMBER 2000

FEATURES

DESCRIPTION

The ISSI IS61SPS25632,IS61SPS25636,IS61SPS51218,

IS61LPS25632, IS61LPS25636, and IS61LPS51218 are

high-speed, low-powersynchronousstaticRAMsdesigned

toprovideaburstable, high-performance, secondarycachefor

thePentium™,680X0™,andPowerPC™microprocessors.

The IS61SPS25632 and IS61LPS25632 are organized as

262,144 words by 32 bits and the IS61SPS25636 and

IS61LPS25636 are organized as 262,144 words by 36 bits.

The IS61SPS51218 and IS61LPS51218 are organized as

524,288 words by 18 bits. Fabricated with ISSI's advanced

CMOS technology, the device integrates a 2-bit burst

counter, high-speed SRAM core, and high-drive capability

outputs into a single monolithic circuit. All synchronous inputs

passthroughregisterscontrolledbyapositive-edge-triggered

single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control using

MODE input

•

Threechipenableoptionforsimpledepthexpansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Single +3.3V, +10%, –5% power supply

• Power-down snooze mode

• 3.3V I/O For SPS

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write

enable (BWE).input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

• 2.5V I/O For LPS

• Single cycle deselect

• Snooze MODE for reduced-power standby

• T version (three chip selects)

• D version (two chip selects)

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

LinearburstisachievedwhenthispinistiedLOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-166*

3.5

-150

3.8

-133

-5

Units

Clock Access Time

Cycle Time

tKC

6.7

7.5

133

100

Frequency

166

150

MHz

*This speed available only in SPS version

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00A

04/17/01

12 3 4 5 6 7...22

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与IS61SPS25636D-166B相关器件

型号	品牌	获取价格	描述	数据表
IS61SPS25636D-166TQ	ISSI	获取价格	Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, TQFP-100
IS61SPS25636D-5B	ISSI	获取价格	Cache SRAM, 256KX36, 5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61SPS25636D-5TQ	ISSI	获取价格	Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100
IS61SPS25636D-5TQI	ISSI	获取价格	Cache SRAM, 256KX36, 5ns, CMOS, PQFP100, TQFP-100
IS61SPS25636T-166TQ	ISSI	获取价格	Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, TQFP-100
IS61SPS51218D-166B	ISSI	获取价格	Cache SRAM, 512KX18, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61SPS51218D-166TQ	ISSI	获取价格	Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, TQFP-100
IS61SPS51218D-5TQ	ISSI	获取价格	Cache SRAM, 512KX18, 5ns, CMOS, PQFP100, TQFP-100
IS61SPS51218T-133TQ	ISSI	获取价格	Cache SRAM, 512KX18, 4ns, CMOS, PQFP100, TQFP-100
IS61SPS51218T-133TQI	ISSI	获取价格	Cache SRAM, 512KX18, 4ns, CMOS, PQFP100, TQFP-100

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