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IS61QDPB42M36-333M3L PDF预览

IS61QDPB42M36-333M3L

更新时间： 2024-02-25 20:09:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器双倍数据速率时钟
页数 文件大小 规格书
28页 669K
描述
72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs

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中文翻译

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IS61QDPB42M36-333M3L 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.59
Is Samacsys：N最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：333 MHz
I/O 类型：SEPARATEJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：17 mm
内存密度：75497472 bit内存集成电路类型：DDR SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：2MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：1.5/1.8,1.8 V认证状态：Not Qualified
座面最大高度：1.7 mm最大待机电流：0.4 A
最小待机电流：1.71 V子类别：SRAMs
最大压摆率：0.85 mA最大供电电压 (Vsup)：1.89 V
最小供电电压 (Vsup)：1.71 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：10
宽度：15 mmBase Number Matches：1

IS61QDPB42M36-333M3L 数据手册

 浏览型号IS61QDPB42M36-333M3L的Datasheet PDF文件第2页浏览型号IS61QDPB42M36-333M3L的Datasheet PDF文件第3页浏览型号IS61QDPB42M36-333M3L的Datasheet PDF文件第4页浏览型号IS61QDPB42M36-333M3L的Datasheet PDF文件第5页浏览型号IS61QDPB42M36-333M3L的Datasheet PDF文件第6页浏览型号IS61QDPB42M36-333M3L的Datasheet PDF文件第7页 
72 Mb (2M x 36 & 4M x 18)  
.
QUADP (Burst of 4) Synchronous SRAMs  
May 2009  
Features  
• 2M x 36 or 4M x 18.  
• +1.8V core power supply and 1.5, 1.8V VDDQ  
used with 0.75, 0.9V VREF  
,
• On-chip delay-locked loop (DLL) for wide data  
valid window.  
.
• HSTL input and output levels.  
• Separate read and write ports with concurrent  
read and write operations.  
• Registered addresses, write and read controls,  
byte writes, data in, and data outputs.  
• Synchronous pipeline read with late write opera-  
tion.  
• Full data coherency.  
• Boundary scan using limited set of JTAG 1149.1  
functions.  
• Double data rate (DDR) interface for read and  
write input ports.  
• Byte write capability.  
• Fixed 4-bit burst for read and write operations.  
• Clock stop support.  
• Fine ball grid array (FBGA) package  
- 15mm x 17mm body size  
- 1mm pitch  
• Two input clocks (K and K) for address and con-  
trol registering at rising edges only.  
- 165-ball (11 x 15) array  
• Two echo clocks (CQ and CQ) that are delivered  
• Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
simultaneously with data.  
Description  
The 72Mb IS61QDPB42M36 and  
• Byte writes for burst addresses 2 and 4  
• Data-in for burst addresses 2 and 4  
IS61QDPB44M18 are synchronous, high-perfor-  
mance CMOS static random access memory  
(SRAM) devices. These SRAMs have separate I/Os,  
eliminating the need for high-speed bus turnaround.  
The rising edge of K clock initiates the read/write  
operation, and all internal operations are self-timed.  
Refer to the Timing Reference Diagram for Truth  
Table on page 8 for a description of the basic opera-  
tions of these QUADP (Burst of 4) SRAMs.  
Byte writes can change with the corresponding data-  
in to enable or disable writes on a per-byte basis. An  
internal write buffer enables the data-ins to be regis-  
tered one cycle after the write address. The first  
data-in burst is clocked one cycle later than the write  
command signal, and the second burst is timed to  
the following rising edge of the K clock. Two full  
clock cycles are required to complete a write opera-  
tion.  
Read and write addresses are registered on alter-  
nating rising edges of the K clock. Reads and writes  
are performed in double data rate. The following are  
registered internally on the rising edge of the K  
clock:  
The device is operated with a single +1.8V power  
supply and is compatible with HSTL I/O interfaces.  
• Read/write address  
• Read enable  
• Write enable  
• Byte writes for burst addresses 1 and 3  
• Data-in for burst addresses 1 and 3  
The following are registered on the rising edge of  
the K clock:  
Integrated Silicon Solution, Inc.  
1
Rev. A  
05/14/09  
1234567...28

中文翻译

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IS61QDPB42M36A1 ISSI

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 		2Mx36 and 4Mx18 configuration available
IS61QDPB42M36A2 ISSI

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 		2Mx36 and 4Mx18 configuration available
IS61QDPB42M36B ISSI

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 		2Mx36 and 4Mx18 configuration available
IS61QDPB42M36B1 ISSI

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 		2Mx36 and 4Mx18 configuration available
IS61QDPB42M36B2 ISSI

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 		2Mx36 and 4Mx18 configuration available

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