IS61QDP2B41M18A
IS61QDP2B451236A
1Mx18 , 512Kx36
18Mb QUAD-P (Burst 4) SYNCHRONOUS SRAM
ADVANCED INFORMATION
SEPTEMBER 2010
(2.0 Cycle Read Latency)
FEATURES
DESCRIPTION
The 18Mb IS61QDP2B451236 and IS61QDP2B41M18 are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these QUAD-P (Burst of 4) SRAMs. Read
and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate.
512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid
window.
Separate read and write ports with concurrent read
and write operations.
Synchronous pipeline read with late write operation.
Double data rate (DDR) interface for read and write
input ports.
2.0 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
The following are registered internally on the rising edge of
the K clock:
Two input clocks (K and K#) for address and control
registering at rising edges only.
Read/write address
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
Read enable
Write enable
Data Valid Pin (QVLD).
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
The following are registered on the rising edge of the K#
clock:
HSTL input and output levels.
Byte writes for burst addresses 2 and 4
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Data-in for burst addresses 2 and 4
Full data coherency.
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the third
and fourth rising edges of the K clock (starting 2.0 cycles
later after read command). The data-outs from the second
and fourth bursts are updated with the third and fourth rising
edges of the K# clock where the read command receives at
the first rising edge of K. Two full clock cycles are required to
complete a read operation.
ODT(On-Die Termination) feature is supported
optionally on Input clocks, Data input, and Control
signals.
The device is operated with a single +1.8V power supply
and is compatible with HSTL I/O interfaces.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
1
5/12/2010
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