IS61QDP2B24M18A/A1/A2
IS61QDP2B22M36A/A1/A2
4Mx18, 2Mx36
FEBRUARY 2014
72Mb QUADP (Burst 2) Synchronous SRAM
(2.0 CYCLE READ LATENCY)
DESCRIPTION
The
FEATURES
2Mx36 and 4Mx18 configuration available.
and
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with EARLY write
operation.
for a description of the basic
Double Data Rate (DDR) interface for read and
write input ports.
operations of these
SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Read and write performed in double data rate.
2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
The following are registered internally on the rising edge of
the K clock:
Two input clocks (K and K#) for address and control
registering at rising edges only.
Read address
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
Read enable
Write enable
Data valid pin (QVLD).
Data-in for early writes
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
The following are registered on the rising edge of the K#
clock:
HSTL input and output interface.
Write address
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Byte writes
Full data coherency.
Data-in for second burst addresses
Boundary scan using limited set of JTAG 1149.1
functions.
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered half a cycle
earlier than the write address. The first data-in burst is
clocked at the same time as the write command signal, and
the second burst is timed to the following rising edge of the
K# clock.
Byte Write capability.
Fine ball grid array (FBGA) package option:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
ODT (On Die Termination) feature is supported
optionally on data input, K/K#, and BWx#.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the second rising
edge of the K# clock (starting two cycles later after read
command). The data-outs from the second bursts are
updated with the third rising edge of the K clock. The K and
K# clocks are used to time the data-outs.
The end of top mark (A/A1/A2) is to define options.
: Don’t care ODT function
and pin connection
1 : Option1
2 : Option2
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interface.
Refer to more detail description at page 6 for each
ODT option.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
1
02/11/2014
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