Datasheet > 存储 > SRAM> IS61QDB42M18-200M3

IS61QDB42M18-200M3

更新时间： 2024-10-13 03:05:07

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路静态存储器双倍数据速率时钟
页数	文件大小	规格书
28页	452K
描述
36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs

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技术参数
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IS61QDB42M18-200M3 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1 MM PITCH, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.71
Is Samacsys：	N	最长访问时间：	0.38 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	17 mm
内存密度：	37748736 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.7 mm
最大待机电流：	0.2 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.5 mA
最大供电电压 (Vsup)：	1.89 V	最小供电电压 (Vsup)：	1.71 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

IS61QDB42M18-200M3 数据手册

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36 Mb (1M x 36 & 2M x 18)

QUAD (Burst of 4) Synchronous SRAMs

ISSI

May 2005

• Two echo clocks (CQ and CQ) that are delivered

Features

simultaneously with data.

• 1M x 36 or 2M x 18.

• +1.8V core power supply and 1.5, 1.8V V_DDQ

used with 0.75, 0.9V V_REF

• On-chip delay-locked loop (DLL) for wide data

valid window.

• HSTL input and output levels.

• Separate read and write ports with concurrent

read and write operations.

• Registered addresses, write and read controls,

byte writes, data in, and data outputs.

• Synchronous pipeline read with late write opera-

tion.

• Full data coherency.

• Boundary scan using limited set of JTAG 1149.1

functions.

• Double data rate (DDR) interface for read and

write input ports.

• Byte write capability.

• Fixed 4-bit burst for read and write operations.

• Clock stop support.

• Fine ball grid array (FBGA) package

- 15mm x 17mm body size

- 1mm pitch

• Two input clocks (K and K) for address and con-

trol registering at rising edges only.

- 165-ball (11 x 15) array

• Two input clocks (C and C) for data output con-

trol.

• Programmable impedance output drivers via 5x

user-supplied precision resistor.

Description

The 36Mb IS61QDB41M36 and

• Byte writes for burst addresses 2 and 4

• Data-in for burst addresses 2 and 4

IS61QDB42M18 are synchronous, high-perfor-

mance CMOS static random access memory

(SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed.

Refer to the Timing Reference Diagram for Truth

Table on page 8 for a description of the basic opera-

tions of these QUAD (Burst of 4) SRAMs.

Byte writes can change with the corresponding data-

in to enable or disable writes on a per-byte basis. An

internal write buffer enables the data-ins to be regis-

tered one cycle after the write address. The first

data-in burst is clocked one cycle later than the write

command signal, and the second burst is timed to

the following rising edge of the K clock. Two full

clock cycles are required to complete a write opera-

tion.

Read and write addresses are registered on alter-

nating rising edges of the K clock. Reads and writes

are performed in double data rate. The following are

registered internally on the rising edge of the K

clock:

During the burst read operation, the data-outs from

the first and third bursts are updated from output

registers off the second and fourth rising edges of

the C clock (starting 1.5 cycles later). The data-outs

from the second and fourth bursts are updated with

the third and fifth rising edges of the C clock. The K

and K clocks are used to time the data-outs when-

ever the C and C clocks are tied high. Two full clock

cycles are required to complete a read operation

• Read/write address

• Read enable

• Write enable

• Byte writes for burst addresses 1 and 3

• Data-in for burst addresses 1 and 3

The following are registered on the rising edge of

the K clock:

The device is operated with a single +1.8V power

supply and is compatible with HSTL I/O interfaces.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/09/04

12 3 4 5 6 7...28

中文翻译

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与IS61QDB42M18-200M3相关器件

型号	品牌	获取价格	描述	数据表
IS61QDB42M18A	ISSI	获取价格	Synchronous pipeline read with late write operation
IS61QDB42M18A-333M3LI	ISSI	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB42M18C-250M3	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA
IS61QDB42M18C-250M3L	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA
IS61QDB42M18C-300M3L	ISSI	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB42M18C-333M3I	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA
IS61QDB42M18C-333M3L	ISSI	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB42M18C-333M3LI	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA
IS61QDB42M36	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs
IS61QDB42M36-250M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 4) Synchronous SRAMs

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