Datasheet > IS61NVP51218A-200B2-TR

IS61NVP51218A-200B2-TR

更新时间： 2024-11-26 09:50:11

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
37页	533K
描述
ZBT SRAM, 512KX18, 3.1ns, CMOS, PBGA119

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AllꢀRead,WriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ

IS61NLP25636A/IS61NVP25636A

IS61NLP51218A/IS61NVP51218Aꢀ

ꢀ

256Kꢀxꢀ36ꢀandꢀ512Kꢀxꢀ18

9Mb,ꢀPIPELINEꢀ'NOꢀWAIT'ꢀSTATEꢀBUSꢀSRAM

AUGUSTꢀ2011

FEATURES

DESCRIPTION

Theꢀ9ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ

low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ

aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ

networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ

organizedꢀasꢀ256Kꢀwordsꢀbyꢀ36ꢀbitsꢀandꢀ512Kꢀꢀwordsꢀbyꢀ18ꢀ

bits,ꢀfabricatedꢀwithꢀISSI'sꢀadvancedꢀCMOSꢀtechnology.

•ꢀ 100ꢀpercentꢀbusꢀutilization

•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControl

•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin

Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ

eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ

writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ

high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ

intoꢀaꢀsingleꢀmonolithicꢀcircuit.

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ

dataꢀandꢀcontrol

ꢀ

•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-

ingꢀMODEꢀinputꢀ

Allꢀsynchronousꢀinputsꢀpassꢀthroughꢀregistersꢀareꢀcontrolledꢀ

byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ

mayꢀbeꢀsuspendedꢀandꢀallꢀsynchronousꢀinputsꢀignoredꢀ

whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ

deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.

•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ

andꢀaddressꢀpipelining

•ꢀ PowerꢀDownꢀmode

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation

input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ

isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ

whenꢀADVꢀisꢀLOW.

•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ

119-ballꢀPBGAꢀpackages

Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ

byꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinputsꢀandꢀwhenꢀWEꢀisꢀ

LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ

written.

•ꢀ Powerꢀsupply:ꢀ

NVP:ꢀV^dd2.5Vꢀ( ꢀ5%),ꢀVddqꢀ2.5Vꢀ( ꢀ5%)

NLP:ꢀV^ddꢀ3.3Vꢀ( ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ( ꢀ5%)

•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackages

•ꢀ Industrialꢀtemperatureꢀavailable

•ꢀ Lead-freeꢀavailable

ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdeﬁnesꢀtheꢀorderꢀofꢀtheꢀburstꢀ

sequence.WhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ

isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ

selected.

FASTꢀACCESSꢀTIME

ꢀ

Symbolꢀ

Parameterꢀ

-250ꢀ

2.6ꢀ

4ꢀ

-200ꢀ

3.1ꢀ

5ꢀ

Units

tkqꢀ

tkcꢀ

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

Frequencyꢀ

250ꢀ

200ꢀ

MHz

liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspeciﬁcationꢀbeforeꢀrelyingꢀonꢀ

anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ

IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀ

failureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsigniﬁcantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀ

assuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:

a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;

b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand

c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774ꢀ

Rev.ꢀ Hꢀ

08/09/2011

12 3 4 5 6 7...37

中文翻译

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与IS61NVP51218A-200B2-TR相关器件

型号	品牌	获取价格	描述	数据表
IS61NVP51218A-200B3	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-200B3I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-200B3I-TR	ISSI	获取价格	ZBT SRAM, 512KX18, 3.1ns, CMOS, PBGA165
IS61NVP51218A-200B3-TR	ISSI	获取价格	ZBT SRAM, 512KX18, 3.1ns, CMOS, PBGA165
IS61NVP51218A-200TQ	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-200TQI	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-200TQI-TR	ISSI	获取价格	ZBT SRAM, 512KX18, 3.1ns, CMOS, PQFP100,
IS61NVP51218A-200TQ-TR	ISSI	获取价格	ZBT SRAM, 512KX18, 3.1ns, CMOS, PQFP100,
IS61NVP51218A-250B2	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP51218A-250B2I	ISSI	获取价格	256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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