Datasheet > IS61NLP51218B-200TQLI-TR

IS61NLP51218B-200TQLI-TR

更新时间： 2024-11-11 20:10:47

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
37页	940K
描述
ZBT SRAM, 512KX18, 3.1ns, CMOS, PQFP100, LQFP-100

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技术参数
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IS61NLP51218B-200TQLI-TR 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LQFP, QFP100,.63X.87	Reach Compliance Code：	compliant
Factory Lead Time：	10 weeks	风险等级：	5.74
最长访问时间：	3.1 ns	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX18	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.6 mm
最小待机电流：	3.135 V	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

IS61NLP51218B-200TQLI-TR 数据手册

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AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheADVꢀ

Long-term Support

World Class Quality

IS61NLP25636B/IS61NVP/NVVP25636B

IS61NLP51218B/IS61NVP/NVVP51218B

256K x 36 and 512K x 18

AUGUST 2019

9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

FEATURES

DESCRIPTION

Theꢀ9ꢀMegꢀproductꢀfamilyꢀfeaturesꢀhigh-speed,ꢀlow-powerꢀ

synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀaꢀburstable,ꢀ

high-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀnetworkingꢀandꢀ

communicationsꢀapplications.ꢀTheyꢀareꢀorganizedꢀasꢀ256Kꢀ

wordsꢀbyꢀ36ꢀbitsꢀandꢀ512Kꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀ

withꢀISSI'sꢀadvancedꢀCMOSꢀtechnology.

•ꢀ 100ꢀpercentꢀbusꢀutilization

•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControl

•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin

Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ

eliminatedꢀwhenꢀtheꢀbusꢀswitchesꢀfromꢀreadꢀtoꢀwrite,ꢀorꢀ

writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ

high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ

intoꢀaꢀsingleꢀmonolithicꢀcircuit.

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ

dataꢀandꢀcontrol

ꢀ

•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-

ingꢀMODEꢀinputꢀ

Allꢀsynchronousꢀinputsꢀpassꢀthroughꢀregistersꢀareꢀcontrolledꢀ

byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ

mayꢀbeꢀsuspendedꢀandꢀallꢀsynchronousꢀinputsꢀignoredꢀ

whenꢀClockꢀEnable,ꢀCKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ

deviceꢀwillꢀholdꢀtheirꢀpreviousꢀvalues.

•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ

andꢀaddressꢀpipelining

•ꢀ PowerꢀDownꢀmode

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ CKEꢀpinꢀtoꢀenableꢀclockꢀandꢀsuspendꢀoperation

input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ

isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ

whenꢀADVꢀisꢀLOW.

•ꢀ JEDECꢀ100-pinꢀQFP,ꢀ165-ballꢀBGAꢀandꢀ119-ballꢀ

BGAꢀpackages

Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ

byꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinputsꢀandꢀwhenꢀWEꢀisꢀ

LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ

written.

•ꢀ Powerꢀsupply:

NLP:ꢀV^ddꢀ3.3Vꢀ(±ꢀ5%),ꢀVddqꢀ3.3V/2.5Vꢀ(±ꢀ5%)

ꢀ NVP:ꢀV^dd2.5Vꢀ(±ꢀ5%),ꢀVddqꢀ2.5Vꢀ(±ꢀ5%)

ꢀ NVVP:ꢀV^dd1.8Vꢀ(±ꢀ5%),ꢀVddqꢀ1.8Vꢀ(±ꢀ5%)

•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackages

•ꢀ Industrialꢀtemperatureꢀavailable

ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdeﬁnesꢀtheꢀorderꢀofꢀtheꢀburstꢀ

sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ

isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ

selected.

•ꢀ Lead-freeꢀavailable

FAST ACCESS TIME

Symbol

Parameter

-250

2.6ꢀ

4ꢀ

-200

3.1ꢀ

5ꢀ

-166

3.5ꢀ

6ꢀ

Units

ꢀ

tkqꢀ

tkcꢀ

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

Frequencyꢀ

250ꢀ

200ꢀ

166ꢀ

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A4

07/19/2019

12 3 4 5 6 7...37

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与IS61NLP51218B-200TQLI-TR相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP51218B-250TQLI	ISSI	获取价格	ZBT SRAM, 512KX18, 2.6ns, CMOS, PQFP100, LQFP-100
IS61NLP51236	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200B2I	ISSI	获取价格	ZBT SRAM, 512KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119
IS61NLP51236-200B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200B3I	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200B3LI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200TQ	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200TQI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-200TQLI	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP51236-250B3	ISSI	获取价格	256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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