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IS61LV6432-8TQI PDF预览

IS61LV6432-8TQI

更新时间： 2024-11-19 23:01:19
品牌 Logo 应用领域
矽成 - ICSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
16页 488K
描述
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

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IS61LV6432-8TQI 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QFP, QFP100,.63X.87Reach Compliance Code：unknown
风险等级：5.88Is Samacsys：N
最长访问时间：8 ns最大时钟频率 (fCLK)：66 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0内存密度：2097152 bit
内存集成电路类型：STANDARD SRAM内存宽度：32
端子数量：100字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
电源：2.5/3.3,3.3 V认证状态：Not Qualified
最大待机电流：0.01 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.15 mA
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

IS61LV6432-8TQI 数据手册

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IS61LV6432  
64K x 32 SYNCHRONOUS  
PIPELINE STATIC RAM  
FEATURES  
DESCRIPTION  
The ICSI IS61LV6432 is a high-speed, low-power synchro-  
nous static RAM designed to provide a burstable, high-perfor-  
mance, secondary cache for the Pentium™, 680X0™, and  
PowerPC™ microprocessors. It is organized as 65,536 words  
by 32 bits, fabricated with ICSI's advanced CMOS technology.  
The device integrates a 2-bit burst counter, high-speed SRAM  
core, and high-drive capability outputs into a single monolithic  
circuit. All synchronous inputs pass through registers con-  
trolled by a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
• Power-down control by ZZ input  
• JEDEC 100-Pin LQFP and PQFP package  
• 3.3V VCC and 2.5V VCCQ for 2.5 I/O's  
• Two Clock enables and one Clock disable to  
eliminate multiple bank bus contention.  
• Control pins mode upon power-up:  
– MODE in interleave burst mode  
– ZZ in normal operation mode  
These control pins can be connected to GNDQ  
or VCCQ to alter their power-up state  
• Industrial temperature available  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3  
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned  
by BWE being LOW. A LOW on GW input would cause all bytes  
to be written.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins. Subsequent burst addresses can be generated internally  
by the IS61LV6432 and controlled by the ADV (burst address  
advance) input pin.  
Asynchronous signals include output enable (OE), sleep mode  
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH  
input on the ZZ pin puts the SRAM in the power-down state.  
When ZZ is pulled LOW (or no connect), the SRAM normally  
operates after three cycles of the wake-up period. A LOW  
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ  
(or no connect) on MODE pin selects INTERLEAVED Burst.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
CLK Access Time  
-166  
5
-133  
5
-117  
5
-5  
5
-6  
6
-7  
7
-8  
8
Unit  
ns  
tKC  
Cycle Time  
6
7.5  
133  
8.5  
117  
10  
100  
12  
83  
13  
75  
15  
66  
ns  
—
Frequency  
166  
MHz  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
1
SSR005-0B  
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