IS61LV6432-133PQ

更新时间： 2024-11-16 23:01:19

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
16页	488K
描述
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

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IS61LV6432-133PQ 数据手册

IS61LV6432

64K x 32 SYNCHRONOUS

PIPELINE STATIC RAM

FEATURES

DESCRIPTION

The ICSI IS61LV6432 is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-perfor-

mance, secondary cache for the Pentium™, 680X0™, and

PowerPC™ microprocessors. It is organized as 65,536 words

by 32 bits, fabricated with ICSI's advanced CMOS technology.

The device integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single monolithic

circuit. All synchronous inputs pass through registers con-

trolled by a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin LQFP and PQFP package

• 3.3V V^CCand 2.5V VCCQ for 2.5 I/O's

• Two Clock enables and one Clock disable to

eliminate multiple bank bus contention.

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

These control pins can be connected to GNDQ

or VCCQ to alter their power-up state

• Industrial temperature available

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3

controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned

by BWE being LOW. A LOW on GW input would cause all bytes

to be written.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated internally

by the IS61LV6432 and controlled by the ADV (burst address

advance) input pin.

Asynchronous signals include output enable (OE), sleep mode

input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH

input on the ZZ pin puts the SRAM in the power-down state.

When ZZ is pulled LOW (or no connect), the SRAM normally

operates after three cycles of the wake-up period. A LOW

input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ

(or no connect) on MODE pin selects INTERLEAVED Burst.

FAST ACCESS TIME

Symbol

tKQ

Parameter

CLK Access Time

-166

-133

-117

-5

-6

-7

-8

Unit

tKC

Cycle Time

7.5

133

8.5

117

100

—

Frequency

166

MHz

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

SSR005-0B

12 3 4 5 6 7...16

中文翻译

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与IS61LV6432-133PQ相关器件

型号	品牌	获取价格	描述	数据表
IS61LV6432-133TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-166PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-166TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-166TQ	ISSI	获取价格	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, TQFP-100
IS61LV6432-5PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-5PQI	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-5PQI	ISSI	获取价格	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61LV6432-5TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-5TQI	ICSI	获取价格	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-5TQI	ISSI	获取价格	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, TQFP-100

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