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IS61LV6424-10TQ PDF预览

IS61LV6424-10TQ

更新时间: 2024-11-16 23:01:19
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
10页 138K
描述
64K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV6424-10TQ 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QFP, QFP100,.63X.87Reach Compliance Code:unknown
风险等级:5.88最长访问时间:10 ns
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0内存密度:1572864 bit
内存集成电路类型:STANDARD SRAM内存宽度:24
端子数量:100字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX24输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.01 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.15 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:QUAD
Base Number Matches:1

IS61LV6424-10TQ 数据手册

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IS61LV6424  
64K x 24 HIGH-SPEED CMOS STATIC RAM  
WITH 3.3V SUPPLY  
FEATURES  
DESCRIPTION  
The ICSI IS61LV6424 is a high-speed, static RAM organized  
as 65,536 words by 24 bits. It is fabricated using ICSI's high-  
performance CMOS technology. This highly reliable process  
coupled with innovative circuit design techniques, yields ac-  
cess times as fast as 9 ns with low power consumption.  
• High-speed access time: 9, 10, 12, 15 ns  
• CMOS low power operation  
594 mW (max.) operating @ 9 ns  
36 mW (max.) CMOS standby  
• TTL compatible interface levels  
• Single 3.3V power supply  
When CE1 is HIGH and CE2 is LOW (deselected), the device  
assumes a standby mode at which the power dissipation can  
be reduced down with CMOS input levels.  
• Fully static operation: no clock or refresh  
required  
Easy memory expansion is provided by using Chip Enable and  
Output Enable inputs, CE1, CE2, and OE. The active LOW  
Write Enable (WE) controls both writing and reading of the  
memory.  
• Three state outputs  
• Available in 100-pin LQFP  
The IS61LV6424 is packaged in the JEDEC standard  
100-pin 14*20*1.4mm LQFP.  
FUNCTIONAL BLOCK DIAGRAM  
V
CC  
GND  
64K x 24  
MEMORY ARRAY  
ROW  
DECODER  
A0-A14  
A15  
X/Y  
V/S  
MULTIPLEX  
ADDRESS  
CONTROL  
COLUMN  
DECODER  
CE1  
CE2  
OE  
CONTROL  
CIRCUIT  
I/O DATA  
I/O0-I/O23  
CIRCUIT  
WE  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
AHSR012-0D  
S2-95  

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