Datasheet > IS61LV6424-10

IS61LV6424-10

更新时间： 2024-11-19 23:01:19

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
10页	138K
描述
64K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

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中文翻译

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IS61LV6424-10 数据手册

IS61LV6424

64K x 24 HIGH-SPEED CMOS STATIC RAM

WITH 3.3V SUPPLY

FEATURES

DESCRIPTION

The ICSI IS61LV6424 is a high-speed, static RAM organized

as 65,536 words by 24 bits. It is fabricated using ICSI's high-

performance CMOS technology. This highly reliable process

coupled with innovative circuit design techniques, yields ac-

cess times as fast as 9 ns with low power consumption.

• High-speed access time: 9, 10, 12, 15 ns

• CMOS low power operation

— 594 mW (max.) operating @ 9 ns

— 36 mW (max.) CMOS standby

• TTL compatible interface levels

• Single 3.3V power supply

When CE1 is HIGH and CE2 is LOW (deselected), the device

assumes a standby mode at which the power dissipation can

be reduced down with CMOS input levels.

• Fully static operation: no clock or refresh

required

Easy memory expansion is provided by using Chip Enable and

Output Enable inputs, CE1, CE2, and OE. The active LOW

Write Enable (WE) controls both writing and reading of the

memory.

• Three state outputs

• Available in 100-pin LQFP

The IS61LV6424 is packaged in the JEDEC standard

100-pin 14*20*1.4mm LQFP.

FUNCTIONAL BLOCK DIAGRAM

GND

64K x 24

MEMORY ARRAY

ROW

DECODER

A0-A14

A15

X/Y

V/S

MULTIPLEX

ADDRESS

CONTROL

COLUMN

DECODER

CE1

CE2

CONTROL

CIRCUIT

I/O DATA

I/O0-I/O23

CIRCUIT

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

AHSR012-0D

S2-95

12 3 4 5 6 7...10

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