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IS61LV3216-20K PDF预览

IS61LV3216-20K

更新时间: 2024-11-16 20:31:11
品牌 Logo 应用领域
矽成 - ICSI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 429K
描述
Standard SRAM, 32KX16, 20ns, CMOS, PDSO44,

IS61LV3216-20K 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOJ, SOJ44,.44Reach Compliance Code:unknown
风险等级:5.86Is Samacsys:N
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J44JESD-609代码:e0
内存密度:524288 bit内存集成电路类型:STANDARD SRAM
内存宽度:16端子数量:44
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ44,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified最大待机电流:0.005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.16 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

IS61LV3216-20K 数据手册

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IS61LV3216  
32K x 16 LOW VOLTAGE CMOS STATIC RAM  
FEATURES  
DESCRIPTION  
1
The ICSI IS61LV3216 is a high-speed, 512K static RAM  
organized as 32,768 words by 16 bits. It is fabricated using  
ICSI's high-performance CMOS technology. This highly reli-  
able process coupled with innovative circuit design techniques,  
yields fast access times with low power consumption.  
• High-speed access time: 10, 12, 15, and 20 ns  
• CMOS low power operation  
— 150 mW (typical) operating  
— 150 µW (typical) standby  
2
• TTL compatible interface levels  
• Single 3.3V ± 10% power supply  
• Fully static operation: no clock or refresh  
required  
• Three state outputs  
• Industrial temperature available  
When CE is HIGH (deselected), the device assumes a standby  
mode at which the power dissipation can be reduced down with  
CMOS input levels.  
3
Easy memory expansion is provided by using Chip Enable and  
Output Enable inputs, CE and OE. The active LOW Write  
Enable (WE) controls both writing and reading of the memory.  
A data byte allows Upper Byte (UB) and Lower Byte (LB)  
access.  
4
• Available in 44-pin 400mil SOJ package and  
44-pin TSOP-2  
5
The IS61LV3216 is packaged in the JEDEC standard 44-pin  
400mil SOJ and 44-pin 400mil TSOP-2.  
FUNCTIONAL BLOCK DIAGRAM  
6
7
32K x 16  
MEMORY ARRAY  
A0-A14  
DECODER  
8
VCC  
GND  
9
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
CIRCUIT  
COLUMN I/O  
I/O8-I/O15  
Upper Byte  
10  
11  
12  
CE  
OE  
WE  
CONTROL  
CIRCUIT  
UB  
LB  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 1997, Integrated Silicon Solution Inc.  
Integrated Circuit Solution Inc.  
1
SR009-0B  

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