Datasheet > IS61LF25632D-6.5TQI

IS61LF25632D-6.5TQI

更新时间： 2024-09-26 05:13:27

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
26页	160K
描述
Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, TQFP-100

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中文翻译

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61LF25632T/D/J

IS61LF25636T/D/J IS61LF51218T/D/J ISSI

256K x 32, 256K x 36, 512K x 18

SYNCHRONOUS FLOW THROUGH

OCTOBER 2002

STATIC RAM

FEATURES

DESCRIPTION

The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are

high-speed, low-power synchronous static RAMs designed to

provide a burstable, high-performance and memories for

commucationandnetworkingapplications.TheIS61LF25632

isorganizedas262,144wordsby32bitsandtheIS61LF25636

isorganizedas262,144wordsby36bits.TheIS61LF51218is

organized as 524,288 words by 18 bits. Fabricated with ISSI's

advanced CMOS technology, the device integrates a 2-bit

burstcounter,high-speedSRAMcore,andhigh-drivecapability

outputs into a single monolithic circuit. All synchronous inputs

pass through registers that are controlled by a positive-edge-

triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global

Write

• Clock controlled, registered address, data

and control

• Interleaved or linear burst sequence control

using MODE input

•

Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

Writecyclesareinternallyself-timedandareinitiatedbytherising

edgeoftheclockinput.Writecyclescanbefromonetofourbytes

wide as controlled by the write control inputs.

• JEDEC 100-Pin TQFP and

119-pin PBGA package

Separatebyteenablesallowindividualbytestobewritten.Byte

write operation is performed by using byte write enable

(BWE).input combined with one or more individual byte write

signals (BWx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the byte write

controls.

• Power Supply

+ 3.3V V^DD

+ 3.3V or 2.5V VDDQ (I/0)

• Snooze MODE for reduced-power standby

• T version (three chip selects)

• J version (PBGA Package with JTAG)

• D version (two chip selects)

• JTAG Boundary Scan for PBGA.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins.Subsequentburstaddressescanbegeneratedinternally

and controlled by the ADV (burst address advance) input pin.

The mode pin is used to select the burst sequence order, Linear

burst is achieved when this pin is tied LOW. Interleave burst is

achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

6.5

7.5

133

7.5

8.5

117

Units

Clock Access Time

Cycle Time

tKC

Frequency

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. A

10/06/02

12 3 4 5 6 7...26

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与IS61LF25632D-6.5TQI相关器件

型号	品牌	获取价格	描述	数据表
IS61LF25632D-7.5B	ISSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LF25632D-7.5TQ	ISSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PQFP100, TQFP-100
IS61LF25632D-7.5TQI	ISSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PQFP100, TQFP-100
IS61LF25632T-7.5TQI	ISSI	获取价格	Cache SRAM, 256KX32, 7.5ns, CMOS, PQFP100, TQFP-100
IS61LF25636A	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF25636A_10	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF25636A-6.5B2	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF25636A-6.5B2I	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF25636A-6.5B3	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF25636A-6.5B3I	ISSI	获取价格	256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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