Datasheet > IS61DDPB22M36A-400M3L

IS61DDPB22M36A-400M3L

更新时间： 2024-11-21 20:10:11

品牌	Logo	应用领域
美国芯成 - ISSI		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
31页	529K
描述
DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

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IS61DDPB22M36A-400M3L 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
Factory Lead Time：	10 weeks	风险等级：	5.16
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	400 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	长度：	17 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	36	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.32 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.8 mA	最大供电电压 (Vsup)：	1.89 V
最小供电电压 (Vsup)：	1.71 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	15 mm	Base Number Matches：	1

IS61DDPB22M36A-400M3L 数据手册

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IS61DDPB24M18A/A1/A2

IS61DDPB22M36A/A1/A2

4Mx18, 2Mx36

ADVANCED INFORMATION

JULY 2012

72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

(2.5 Cycle Read Latency)

FEATURES

DESCRIPTION

The 72Mb IS61DDPB22M36A/A1/A2 and



2Mx36 and 4Mx18 configuration available.

IS61DDPB24M18A/A1/A2 are synchronous, high-

performance CMOS static random access memory (SRAM)

devices. These SRAMs have a common I/O bus. The rising

edge of K clock initiates the read/write operation, and all

internal operations are self-timed. Refer to the Timing

Reference Diagram for Truth Table for a description of the

basic operations of these DDR-IIP (Burst of 2) CIO SRAMs.

On-chip Delay-Locked Loop (DLL) for wide data

valid window.



Common I/O read and write ports.

Synchronous pipeline read with self-timed late write

operation.



Double Data Rate (DDR) interface for read and

write input ports.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate.



2.5 cycle read latency.

Fixed 2-bit burst for read and write operations.

Clock stop support.

The following are registered internally on the rising edge of

the K clock:

Two input clocks (K and K#) for address and control

registering at rising edges only.



Read/write address



Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

Read enable

+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.

Write enable

Byte writes



HSTL input and output interface.

Data-in for first burst addresses

Data-Out for second burst addresses

Registered addresses, write and read controls, byte

writes, data in, and data outputs.

The following are registered on the rising edge of the K#

clock:



Full data coherency.



Byte writes

Boundary scan using limited set of JTAG 1149.1

functions.

Data-in for second burst addresses

Data-Out for first burst addresses



Byte write capability.

Fine ball grid array (FBGA) package:

13mm x 15mm & 15mm x 17mm body size

165-ball (11 x 15) array

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock.



Programmable impedance output drivers via 5x

user-supplied precision resistor.



Data Valid Pin (QVLD).

ODT (On Die Termination) feature is supported

optionally on data input, K/K#, and BW_x#.

During the burst read operation, the data-outs from the first

bursts are updated from output registers of the third rising

edge of the K# clock (starting two and half cycles later after

read command). The data-outs from the second burst are

updated with the fourth rising edge of the K clock where read

command receives at the first rising edge of K.



The end of top mark (A/A1/A2) is to define options.

IS61DDPB22M36A : Don’t care ODT function and

pin connection

IS61DDPB22M36A1 : Option1

IS61DDPB22M36A2 : Option2

Refer to more detail description at page 6 for each

ODT option.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00A

7/05/2012

12 3 4 5 6 7...31

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与IS61DDPB22M36A-400M3L相关器件

型号	品牌	获取价格	描述	数据表
IS61DDPB22M36B	ISSI	获取价格	Fixed 2-bit burst for read and write operations
IS61DDPB22M36B1	ISSI	获取价格	Fixed 2-bit burst for read and write operations
IS61DDPB22M36B2	ISSI	获取价格	Fixed 2-bit burst for read and write operations
IS61DDPB24M18-375M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
IS61DDPB24M18-375M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
IS61DDPB24M18-400M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
IS61DDPB24M18-400M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burst of 2) CIO Synchronous SRAMs
IS61DDPB24M18A	ISSI	获取价格	4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18A/A1/A2	ISSI	获取价格	4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18A1-550M3I	ISSI	获取价格	DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, LFBGA-165

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