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IS61C512 PDF预览

IS61C512

更新时间: 2024-11-29 04:44:47
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
8页 425K
描述
64K x 8 HIGH-SPEED CMOS STATIC RAM

IS61C512 数据手册

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IS61C512  
64K x 8 HIGH-SPEED CMOS STATIC RAM  
FEATURES  
DESCRIPTION  
The ICSI IS61C512 is a very high-speed, low power, 65,536  
word by 8-bit CMOS static RAMs. They are fabricated using  
ICSI's high-performance CMOS technology. This highly  
reliable process coupled with innovative circuit design  
techniques, yields higher performance and low power con-  
sumption devices.  
• Pin compatible with 128K x 8 devices  
• High-speed access time: 15, 20, 25, 35 ns  
Low active power: 500 mW (typical)  
• Low standby power  
— 250 µW (typical) CMOS standby  
• Output Enable (OE) and two Chip Enable  
(CE1 and CE2) inputs for ease in applications  
• Fully static operation: no clock or refresh  
required  
• TTL compatible inputs and outputs  
• Single 5V (±10%) power supply  
When CE1 is HIGH or CE2 is LOW (deselected), the device  
assumes a standby mode at which the power dissipation can  
be reduced down to 1 mW (typical) with CMOS input levels.  
Easy memory expansion is provided by using two Chip Enable  
inputs, CE1 and CE2. The active LOW Write Enable (WE)  
controls both writing and reading of the memory.  
The IS61C512 is available in 32-pin 300mil DIP, SOJ and  
8*20mm TSOP-1 packages.  
FUNCTIONAL BLOCK DIAGRAM  
512 X 1024  
MEMORY ARRAY  
A0-A15  
DECODER  
VCC  
GND  
I/O  
DATA  
COLUMN I/O  
I/O0-I/O7  
CIRCUIT  
CE1  
CE2  
CONTROL  
CIRCUIT  
OE  
WE  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
1
SR011-0B  

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