Datasheet > IS61C3216B-20TI

IS61C3216B-20TI

更新时间： 2024-11-28 23:59:47

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
8页	75K
描述
x16 SRAM

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IS61C3216B-20TI 数据手册

IS61C3216B

ISSI^®

DECEMBER 2000

32K x 16 HIGH-SPEED CMOS STATIC RAM

FEATURES

DESCRIPTION

The ISSI IS61C3216B is a high-speed, 512K static RAM

organized as 32,768 words by 16 bits. It is fabricated using

ISSI's high-performance CMOS technology. This highly reli-

able process coupled with innovative circuit design tech-

niques, yields fast access times with low power consumption.

• High-speed access time: 10, 12, 15, and 20 ns

• CMOS low power operation

— 450 mW (typical) operating

— 250 µW (typical) standby

• TTL compatible interface levels

• Single 5V 10% power supply

• I/O compatible with 3.3V device

The device is active when CE is HIGH. When CE is LOW

(deselected), the device assumes a standby mode at which

the power dissipation can be reduced down to 250 µW

(typical) with CMOS input levels.

• Fully static operation: no clock or refresh

required

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs, CE and OE. The active LOW Write

Enable(WE)controlsbothwritingandreadingofthememory.A

data byte allows Upper Byte (UB) and Lower Byte (LB)

access.

• Three state outputs

• Industrialtemperatureavailable

• Available in 44-pin 400-mil SOJ package and

44-pin TSOP (Type II)

The IS61C3216B is packaged in the JEDEC standard 44-pin

400-mil SOJ and 44-pin TSOP (Type II).

FUNCTIONAL BLOCK DIAGRAM

32K x 16

MEMORY ARRAY

A0-A14

DECODER

VCC

GND

I/O0-I/O7

Lower Byte

I/O

DATA

COLUMN I/O

CIRCUIT

I/O8-I/O15

Upper Byte

CONTROL

CIRCUIT

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

12 3 4 5 6 7 8

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