576Mb: x18, x36 RLDRAM 3
Features
RLDRAM 3
IS49RL18320 – 2 Meg x 18 x 16 Banks
IS49RL36160 – 1 Meg x 36 x 16 Banks
Options
Features
t
• Clock cycle and RC timing
• 1066 MHz DDR operation (2133 Mb/s/ball data
rate)
• 76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock
frequency)
• Organization
– 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)
– 16 banks
• 1.2V center-terminated push/pull I/O
• 2.5V VEXT, 1.35V VDD, 1.2V VDDQ I/O
• Reduced cy cle time ( RC (MIN) = 8 - 12ns)
• SDR addressing
• Programmable READ/WRITE latency (RL/WL) and
burst length
t
– 0.93ns and RC (MIN) = 8ns
(RL3-2133)
– 0.93ns and RC (MIN) = 10ns
(RL3-2133)
– 1.07ns and RC (MIN) = 8ns
(RL3-1866)
– 1.07ns and tRC (MIN) = 10ns
(RL3-1866)
t
t
t
– 1.25ns and RC (MIN) = 10ns
t
(RL3-1600)
– 1.25ns and tRC (MIN) = 12ns
(RL3-1600)
• Configuration
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Free-running differential input data clocks (DKx,
DKx#) and output data clocks (QKx, QKx#)
• On-die DLL generates CK edge-aligned data and
differential output data clock signals
• 64ms refresh (128K refresh per 64ms)
• 168-ball FBGA package
– 32 Meg x 18
– 16 Meg x 36
• Operating temperature
– Commercial (TC = 0° to +95°C)
– Industrial (TC = –40°C to +95°C)
• Package
– 168-ball FBGA
– 168-ball FBGA (Pb-free)
• Revision
• 40Ω or 60Ω matched impedance outputs
• Integrated on-die termination (ODT)
• Single or multibank writes
• Extended operating range (200–1066 MHz)
• READ training register
• Multiplexed and non-multiplexed addressing capa-
bilities
• Mirror function
• Output driver and ODT calibration
• JTAG interface (IEEE 1149.1-2001)
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specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any
information, products or services described herein. Customers are advised to obtain the latest version of this device specification
before relying on any published information and before placing orders for products.
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1
Integrated Silicon Solution, Inc. — www.issi.com
01/17/2012