Datasheet > IS43DR81280

IS43DR81280

更新时间： 2024-11-27 11:59:31

品牌	Logo	应用领域
美国芯成 - ISSI		动态存储器双倍数据速率
页数	文件大小	规格书
28页	863K
描述
1Gb (x8, x16) DDR2 SDRAM

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中文翻译

获取价格

数据手册

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IS43DR81280 数据手册

IS43/46DR81280, IS43/46DR16640

PRELIMINARY INFORMATION

MARCH 2010

1Gb (x8, x16) DDR2 SDRAM

FEATURES

•

Clock frequency up to 533MHz

8 internal banks for concurrent operation

4‐bit prefetch architecture

Programmable CAS Latency: 3, 4, 5, 6 and 7

Programmable Additive Latency: 0, 1, 2, 3, 4, 5

and 6

•

Bidirectional differential Data Strobe (Single‐

ended data‐strobe is an optional feature)

On‐Chip DLL aligns DQ and DQs transitions with

CK transitions

DQS# can be disabled for single‐ended data

strobe

•

Read Data Strobe supported (x8 only)

Differential clock inputs CK and CK#

VDD and VDDQ = 1.8V ± 0.1V

PASR (Partial Array Self Refresh)

SSTL_18 interface

tRAS lockout supported

Operating temperature:

Commercial (T_A= 0°C to +70°C ; T_C= 0°C to 85°C)

Industrial (T_A= ‐40°C to +85°C; T_C= ‐40°C to 95°C)

Automotive, A1 (T_A= ‐40°C to +85°C; T_C= ‐40°C to

95°C)

•

Write Latency = Read Latency‐1

Programmable Burst Sequence: Sequential or

Interleave

Programmable Burst Length: 4 and 8

Automatic and Controlled Precharge Command

Power Down Mode

•

Auto Refresh and Self Refresh

Refresh Interval: 7.8 μs (8192 cycles/64 ms)

OCD (Off‐Chip Driver Impedance Adjustment)

ODT (On‐Die Termination)

Weak Strength Data‐Output Driver Option

OPTIONS

ADDRESS TABLE

Parameter

128Mx8

A0‐A13

A0‐A9

BA0‐BA2

A10

64Mx16

A0‐A12

A0‐A9

BA0‐BA2

A10

• Configuration:

Row Addressing

Column Addressing

Bank Addressing

Precharge Addressing

−

128Mx8 (16M x 8 x 8 banks)

64Mx16 (8M x 16 x 8 banks)

• Package:

−

60‐ball FBGA for x8

84‐ball FBGA for x16

Clock Cycle Timing

‐37C

‐3D

‐25E

‐25D

‐19F

Units

Speed Grade

CL‐tRCD‐tRP

tCK (CL=3)

DDR2‐533C

DDR2‐667D

DDR2‐800E

DDR2‐800D

DDR2‐1066F

4‐4‐4

5‐5‐5

6‐6‐6

5‐5‐5

7‐7‐7

tCK

tCK (CL=4)

3.75

tCK (CL=5)

3.75

266

2.5

400

tCK (CL=6)

2.5

400

2.5

tCK (CL=7)

1.875

533

Frequency (max)

333

MHz

Note: The ‐37C device specification is shown for reference only.

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the

latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. 00A, 3/17/2010

12 3 4 5 6 7...28

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与IS43DR81280相关器件

型号	品牌	获取价格	描述	数据表
IS43DR81280-25DBLI	ISSI	获取价格	DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA60, LEAD FREE, FBGA-60
IS43DR81280A	ISSI	获取价格	1Gb (x8, x16) DDR2 SDRAM
IS43DR81280A-25DBLI	ISSI	获取价格	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 13.65 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD F
IS43DR81280A-25DBLI-TR	ISSI	获取价格	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 13.65 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD F
IS43DR81280A-25EBL-TR	ISSI	获取价格	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 13.65 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD F
IS43DR81280A-3DBLI-TR	ISSI	获取价格	DDR DRAM, 128MX8, 0.45ns, CMOS, PBGA60, 8 X 13.65 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD
IS43DR81280A-3DBL-TR	ISSI	获取价格	DDR DRAM, 128MX8, 0.45ns, CMOS, PBGA60, 8 X 13.65 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD
IS43DR81280B	ISSI	获取价格	1Gb (x8, x16) DDR2 SDRAM
IS43DR81280B-25DBL	ISSI	获取价格	DDR DRAM, 128MX8, 0.4ns, CMOS, PBGA60, 8 X 10.50 MM, 1.20 MM HEIGHT, LEAD FREE, TWBGA-60
IS43DR81280B-25DBLI	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA

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