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IS42VM32160D-75BLI PDF预览

IS42VM32160D-75BLI

更新时间: 2024-11-13 20:08:23
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器内存集成电路
页数 文件大小 规格书
27页 311K
描述
Synchronous DRAM, 16MX32, 6ns, CMOS, PBGA90, 8 X 13 MM, LEAD FREE, MO-207, TFBGA-90

IS42VM32160D-75BLI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:DSBGA
包装说明:TFBGA, BGA90,9X15,32针数:90
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.28Factory Lead Time:10 weeks
风险等级:5.36访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PBGA-B90
JESD-609代码:e1长度:13 mm
内存密度:536870912 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:32湿度敏感等级:3
功能数量:1端口数量:1
端子数量:90字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16MX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA90,9X15,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.00001 A子类别:DRAMs
最大压摆率:0.1 mA最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:8 mmBase Number Matches:1

IS42VM32160D-75BLI 数据手册

 浏览型号IS42VM32160D-75BLI的Datasheet PDF文件第2页浏览型号IS42VM32160D-75BLI的Datasheet PDF文件第3页浏览型号IS42VM32160D-75BLI的Datasheet PDF文件第4页浏览型号IS42VM32160D-75BLI的Datasheet PDF文件第5页浏览型号IS42VM32160D-75BLI的Datasheet PDF文件第6页浏览型号IS42VM32160D-75BLI的Datasheet PDF文件第7页 
IS42/45VM32160D  
4M x 32Bits x 4Banks Mobile Synchronous DRAM  
Description  
These IS42/45VM32160D are mobile 536,870,912 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 32 bits.  
These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are  
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input  
and output voltage levels are compatible with LVCMOS.  
Features  
. JEDEC standard 1.8V power supply  
• Auto refresh and self refresh  
• Internal 4 banks operation  
• Burst Read Single Write operation  
• Special Function Support  
• All pins are compatible with LVCMOS interface  
• 8K refresh cycle / 64ms  
- PASR(Partial Array Self Refresh)  
• Programmable Burst Length and Burst Type  
- 1, 2, 4, 8 or Full Page for Sequential Burst  
- 4 or 8 for Interleave Burst  
- Auto TCSR(Temperature Compensated Self Refresh)  
- Programmable Driver Strength Control  
- Full Strength or 1/2, 1/4 or 1/8 of Full Strength  
- Deep Power Down Mode  
• Programmable CAS Latency : 2,3 clocks  
• All inputs and outputs referenced to the positive edge of the  
system clock  
• Automatic precharge, includes CONCURRENT Auto Precharge  
Mode and controlled Precharge  
• Data mask function by DQM  
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its  
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services  
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information  
and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or  
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or  
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to  
its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
1
www.issi.com - DRAM@issi.com  
Rev. A | Apr. 2012  

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