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IS42VM32160C-75BL PDF预览

IS42VM32160C-75BL

更新时间: 2024-11-14 04:22:07
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器
页数 文件大小 规格书
17页 330K
描述
Synchronous DRAM, 16MX32, 5.4ns, CMOS, PBGA90, 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, MS-207, FBGA-90

IS42VM32160C-75BL 数据手册

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IS42VM32160C  
16Mx32  
Advanced Information  
FEBRUARY 2009  
512Mb Mobile Synchronous DRAM  
FEATURES:  
DESCRIPTION:  
ISSI's IS42VM32160C is a 512Mb Mobile Synchronous  
DRAMꢀconfiguredꢀasꢀaꢀquadꢀ4Mꢀx32ꢀDRAM.ꢀItꢀachievesꢀ  
high-speed data transfer using a pipeline architecture  
with a synchronous interface. All inputs and outputs sig-  
nals are registered on the rising edge of the clock input,  
CLK. The 512Mb SDRAM is internally configured by  
stackingꢀtwoꢀ256Mb,ꢀ16Mx16ꢀdevices.ꢀEachꢀofꢀtheꢀ4Mꢀ  
x32ꢀbanksꢀisꢀorganizedꢀasꢀ8192ꢀrowsꢀbyꢀ512ꢀcolumnsꢀ  
by 32 bits.  
•ꢀ Fully synchronous; all signals referenced to a  
positive clock edge  
•ꢀ Internal bank for hiding row access and pre-  
charge  
•ꢀ Programmable CAS latency: 2, 3  
•ꢀ Programmable Burst Length: 1, 2, 4, 8, and Full  
Page  
•ꢀ Programmable Burst Sequence:  
•ꢀ Sequential and Interleave  
•ꢀ Auto Refresh (CBR)  
•ꢀ TCSR (Temperature Compensated Self Refresh)  
KEY TIMING PARAMETERS  
Parameter  
-75  
-10  
Unit  
•ꢀ PASR (Partial Arrays Self Refresh): 1/16, 1/8,  
1/4, 1/2, and Full  
•ꢀ Deep Power Down Mode (DPD)  
•ꢀ Driver Strength Control (DS): 1/4, 1/2, and Full  
CLK Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
CLK Frequency  
CAS Latency = 3  
CAS Latency = 2  
Access Time from CLK  
CAS Latency = 3  
CAS Latency = 2  
7.5  
9.6  
10  
12  
ns  
ns  
OPTIONS:  
•ꢀ Configuration:ꢀ16Mx32  
•ꢀ PowerꢀSupply:  
IS42VMxxxꢀ-ꢀVd d /Vd d q = 1.8V  
•ꢀ Package:ꢀ90ꢀBallꢀBGAꢀ(8mmx13mm)  
•ꢀ TemperatureꢀRange:ꢀ  
Commercial (0oC to +70oC)  
Industrial (-40oC to +85oC)  
133  
104  
100  
83  
Mhz  
Mhz  
5.4  
8.0  
8.0  
9.0  
ns  
ns  
•ꢀ Dieꢀrevision:ꢀC  
ADDRESS TABLE  
Parameter  
16Mx32  
Configuration  
4Mꢀxꢀ32ꢀxꢀ4ꢀbanks  
BA0, BA1  
A10/AP  
Bank Address Pins  
Autoprecharge Pins  
Row Addresses  
Column Addresses  
Refresh Count  
A0 – A12  
A0 – A8  
8K / 64ms  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc.  
1
Rev. 00A  
02/10/09  

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