Datasheet > IS41C16256

IS41C16256

更新时间： 2024-10-01 22:48:03

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
20页	211K
描述
256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS41C16256 数据手册

IS41C16256

IS41LV16256

256K x 16 (4-MBIT) DYNAMIC RAM

WITH EDO PAGE MODE

DESCRIPTION

FEATURES

The ICSI IS41C16256 and IS41LV16256 is a 262,144 x 16-

bit high-performance CMOS Dynamic Random Access Memo-

ries. The IS41C16256 offer an accelerated cycle access

called EDO Page Mode. EDO Page Mode allows 512 random

accesses within a single row with access cycle time as short

as 10 ns per 16-bit word. The Byte Write control, of upper and

lower byte, makes the IS41C16256 ideal for use in

16-, 32-bit wide data bus systems.

• Extended Data-Out (EDO) Page Mode access cycle

• TTL compatible inputs and outputs; tristate I/O

• Refresh Interval: 512 cycles /8 ms

• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),

Hidden

• Single power supply:

5V ± 10% (IS41C16256)

3.3V ± 10% (IS41LV16256)

• Byte Write and Byte Read operation via two CAS

• Industrial Temperature Range -40^oC to 85^oC

These features make the IS41C16256and IS41LV16256 ideally

suited for high-bandwidth graphics, digital signal processing,

high-performance computing systems, and peripheral

applications.

The IS41C16256 is packaged in a 40-pin 400mil SOJ and

400mil TSOP-2.

KEY TIMING PARAMETERS

Parameter

-25(5V)

-35

-50

-60

Unit

Max. RAS Access Time (tRAC)

Max. CAS Access Time (tCAC)

Max. Column Address Access Time (tAA)

Min. EDO Page Mode Cycle Time (tPC)

Min. Read/Write Cycle Time (tRC)

110

PIN CONFIGURATIONS

40-Pin TSOP-2

40-Pin SOJ

PIN DESCRIPTIONS

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

GND

A0-A8

I/O0-15

Address Inputs

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

Data Inputs/Outputs

Write Enable

Output Enable

RAS

UCAS

LCAS

Vcc

Row Address Strobe

Upper Column Address Strobe

Lower Column Address Strobe

Power

I/O8

RAS

LCAS

UCAS

LCAS

UCAS

RAS

GND

Ground

No Connection

VCC

GND

VCC

GND

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

DR001-0E 01/25/2002

12 3 4 5 6 7...20

中文翻译

下载PDF

与IS41C16256相关器件

型号	品牌	获取价格	描述	数据表
IS41C16256-25K	ICSI	获取价格	256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-25KI	ICSI	获取价格	256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-25K-TR	ISSI	获取价格	DRAM
IS41C16256-25T	ICSI	获取价格	256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-25TI	ICSI	获取价格	256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-25T-TR	ISSI	获取价格	DRAM
IS41C16256-28K	ETC	获取价格	x16 EDO Page Mode DRAM
IS41C16256-28T	ETC	获取价格	x16 EDO Page Mode DRAM
IS41C16256-35K	ISSI	获取价格	256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
IS41C16256-35K	ICSI	获取价格	256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

与IS41C16256相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

38
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

32
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

29
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

40

产品中心

服务支持

精选活动

关于我们

帮助中心

IS41C16256

IS41C16256 数据手册

与IS41C16256相关器件

与IS41C16256相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS41C16256

IS41C16256 数据手册

与IS41C16256相关器件

与IS41C16256相关文章

您还可以找

您在本页遇到什么问题？