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IS41C16100-60KE PDF预览

IS41C16100-60KE

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IS41C16100-60KE 数据手册

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®
IS41C16100  
IS41LV16100  
1M x 16 (16-MBIT) DYNAMIC RAM  
WITH EDO PAGE MODE  
ISSI  
April 2003  
FEATURES  
DESCRIPTION  
• TTL compatible inputs and outputs; tristate I/O  
The ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit  
high-performance CMOS Dynamic Random Access Memories.  
ThesedevicesofferanacceleratedcycleaccesscalledEDOPage  
Mode. EDO Page Mode allows 1,024 random accesses within a  
singlerowwithaccesscycletimeasshortas20nsper16-bitword.  
The Byte Write control, of upper and lower byte, makes the  
IS41C16100idealforusein16-bitand32-bitwidedatabussystems.  
• Refresh Interval:  
— Auto refresh Mode: 1,024 cycles /16 ms  
RAS-Only, CAS-before-RAS (CBR), and Hidden  
— Self refresh Mode - 1,024 cycles / 128ms  
• JEDEC standard pinout  
ThesefeaturesmaketheIS41C16100andIS41LV16100ideallysuited  
for high-bandwidth graphics, digital signal processing, high-  
performancecomputingsystems,andperipheralapplications.  
• Single power supply:  
— 5V ± 10% (IS41C16100)  
— 3.3V ± 10% (IS41LV16100)  
TheIS41C16100andIS41LV16100arepackagedina42-pin400-  
milSOJand400-mil50-(44-)pinTSOP(TypeII).Thelead-free400-  
mil50-(44-)optionisavailabletoo.  
• Byte Write and Byte Read operation via two CAS  
• Industrail Temperature Range -40oC to 85oC  
KEY TIMING PARAMETERS  
Parameter  
-50  
50  
13  
25  
20  
84  
-60  
60  
Unit  
ns  
PIN CONFIGURATIONS  
Max. RAS Access Time (tRAC)  
Max. CAS Access Time (tCAC)  
Max. Column Address Access Time (tAA)  
Min. EDO Page Mode Cycle Time (tPC)  
Min. Read/Write Cycle Time (tRC)  
50(44)-Pin TSOP (Type II)  
42-PinSOJ  
15  
ns  
30  
ns  
25  
ns  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
GND  
I/O15  
I/O14  
I/O13  
I/O12  
GND  
I/O11  
I/O10  
I/O9  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
1
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
GND  
I/O15  
I/O14  
I/O13  
I/O12  
GND  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
2
2
104  
ns  
3
3
4
4
5
5
6
PIN DESCRIPTIONS  
6
7
7
8
8
A0-A9  
I/O0-15  
WE  
Address Inputs  
Data Inputs/Outputs  
Write Enable  
9
9
10  
11  
I/O8  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
NC  
NC  
NC  
WE  
RAS  
NC  
NC  
A0  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
NC  
NC  
LCAS  
UCAS  
OE  
OE  
Output Enable  
LCAS  
UCAS  
OE  
WE  
RAS  
NC  
RAS  
UCAS  
LCAS  
Vcc  
Row Address Strobe  
A9  
A9  
Upper Column Address Strobe  
Lower Column Address Strobe  
Power  
NC  
A8  
A8  
A0  
A7  
A7  
A1  
A6  
A1  
A6  
A2  
A5  
A2  
A5  
A3  
A4  
A3  
A4  
GND  
NC  
Ground  
VCC  
GND  
VCC  
GND  
No Connection  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
IIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
R e v .  
I
04/16/03  

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