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IS25C128-2WI PDF预览

IS25C128-2WI

更新时间: 2024-09-20 04:23:03
品牌 Logo 应用领域
美国芯成 - ISSI 可编程只读存储器
页数 文件大小 规格书
17页 138K
描述
128K-bit/ 256K-bit SPI SERIAL ELECTRICALLY ERASABLE PROM

IS25C128-2WI 数据手册

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®
IS25C128  
IS25C256  
128K-bit/ 256K-bit SPI SERIAL  
ELECTRICALLY ERASABLE PROM  
ISSI  
AdvancedInformation  
JULY2006  
FEATURES  
• SerialPeripheralInterface(SPI)Compatible  
— Supports SPI Modes 0 (0,0) and 3 (1,1)  
• LowpowerCMOS  
— Active current less than 3.0 mA (2.5V)  
— Standby current less than 20 µA (2.5V)  
• Low-voltageOperation  
— Vcc = 1.8V to 5.5V  
• Block Write Protection  
— Protect 1/4, 1/2, or Entire Array  
• 64 byte page write mode  
DESCRIPTION  
TheIS25C128andIS25C256areelectricallyerasable  
PROM devices that use the Serial Peripheral Interface  
(SPI) for communications. The IS25C128 is 128Kbit  
(16K x 8) and the IS25C256 is 256Kbit (32K x 8). The  
IS25C128/256 EEPROMs are offered in a wide  
operating voltage range of 1.8V to 5.5V for compatibility  
with most application voltages. ISSI designed the  
IS25C128/256 to be an efficient SPI EEPROM solution.  
The devices are packaged in 8-pin JEDEC SOIC, 8-pin  
EIAJ SOIC, and 8-pin PDIP.  
— Partial page writes allowed  
• 2.1 MHz Clock Rate (5V)  
• Self timed write cycles  
— 5ms max @ 2.5V  
• High-reliability  
— Endurance: 1,000,000 cycles per byte  
— Data retention: 100 years  
• 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin PDIP  
packagesavailable  
• IndustrialandAutomotivetemperatureranges  
• Lead-freeavailable  
ThefunctionalfeaturesoftheIS25C128/256allowthem  
to be among the most advanced serial non-volatile  
memories available. Each device has a Chip-Select  
(CS) pin, and a 3-wire interface of Serial Data In (SI),  
Serial Data Out (SO), and Serial Clock (SCK). While  
the3-wireinterfaceoftheIS25C128/256providesfor  
high-speed access, a HOLD pin allows the memories to  
ignore the interface in a suspended state; later the  
HOLD pinre-activatescommunicationwithoutre-  
initializing the serial sequence. A Status Register  
facilitates a flexible write protection mechanism, and a  
device-readybit(RDY).  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
IntegratedSiliconSolution,Inc.1-800-379-4774  
1
Advanced Information Rev. 00E  
06/13/06  

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