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IS24L256-2WLI PDF预览

IS24L256-2WLI

更新时间： 2024-11-21 04:07:03
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
15页 113K
描述
128K-bit/ 256K-bit 2-WIRE SERIAL CMOS EEPROM

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中文翻译

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IS24L256-2WLI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.84
Is Samacsys：N最大时钟频率 (fCLK)：1 MHz
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：5.29 mm内存密度：262144 bit
内存集成电路类型：EEPROM内存宽度：8
湿度敏感等级：3功能数量：1
端子数量：8字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.16 mm串行总线类型：I2C
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.8 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：5.25 mm
最长写入周期时间 (tWC)：5 msBase Number Matches：1

IS24L256-2WLI 数据手册

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®
IS24L128  
IS24L256  
ISSI  
128K-bit/ 256K-bit  
2-WIRE SERIAL CMOS EEPROM  
ADVANCEDINFORMATION  
APRIL2006  
FEATURES  
DESCRIPTION  
• Two-Wire Serial Interface, I2CTM compatible  
–Bi-directional data transfer protocol  
The IS24L128 and IS24L256 are electrically erasable  
PROM devices that use the standard 2-wire interface  
for communications. The IS24L128 and IS24CL256  
contain a memory array of 128K-bits (16K x 8) and  
256K-bits (32 x 8), respectively. Each device is  
organized into 64 byte pages for page write mode.  
• Low Voltage and Standard Voltage Operation  
–Vcc = 1.8V to 3.6V  
• 400 KHz (1.8V) and 1 MHz (2.5V, 2.7V, 3.6V)  
compatibility  
• Low Power CMOS Technology  
–Active Current less than 3 mA (3.6V)  
–Stanby Current less than 3 µA (3.6V)  
–Standby Current less than 1 µA (1.8V)  
• Hardware Data Protection  
–Write Protect Pin  
This EEPROM operates in a voltage range of 1.8V to  
3.6V for low voltage and standard voltage application  
levels. ISSI designed this device family to be a  
practical, low-power 2-wire EEPROM solution. The  
devices are available in 8-pin PDIP, 8-pin (JEDEC)  
SOIC, and 8-pin (EIAJ) SOIC packages.  
The IS24L128/256 maintains compatibility with the  
popular 2-wire bus protocol, so it is easy to design into  
applications implementing this bus type. The simple  
bus consists of the Serial Clock wire (SCL) and the  
Serial Data wire (SDA). Using the bus, a Master device  
such as a microcontroller is usually connected to one  
or more Slave devices such as the IS24L128/256. The  
bit stream over the SDA line includes a series of bytes,  
which identifies a particular Slave device, an  
instruction, an address within that Slave device, and a  
series of data, if appropriate. The IS24L128/256 has a  
Write Protect pin (WP) to allow blocking of any write  
instruction transmitted over the bus.  
• Sequential Read Feature  
• Filtered Inputs for Noise Suppression  
• Self time write cycle with auto clear  
–5 ms max @ 1.8V  
• Organization:  
IS24L128–16Kx8 (256 pages of 64 bytes)  
IS24L256–32Kx8 (512 pages of 64 bytes)  
• 64 Byte Page Write Buffer  
• High Reliability  
–Endurance: 1,000,000 Cycles  
–Data Retention: 40 Years  
• Industrial temperature range  
• 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-pin  
(EIAJ) SOIC packages  
• Lead-free available  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
ADVANCEDINFORMATION Rev. 00B  
03/21/06  
1234567...15

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